diff --git a/src/amd/common/ac_nir.c b/src/amd/common/ac_nir.c
index 1c9d7d95efc..b06eadfe0d3 100644
--- a/src/amd/common/ac_nir.c
+++ b/src/amd/common/ac_nir.c
@@ -220,6 +220,18 @@ lower_intrinsic_to_arg(nir_builder *b, nir_instr *instr, void *state)
          replacement = ac_nir_load_arg(b, s->args, s->args->local_invocation_ids);
       }
       break;
+   case nir_intrinsic_load_first_vertex:
+      replacement = ac_nir_load_arg(b, s->args, s->args->base_vertex);
+      break;
+   case nir_intrinsic_load_base_instance:
+      replacement = ac_nir_load_arg(b, s->args, s->args->start_instance);
+      break;
+   case nir_intrinsic_load_draw_id:
+      replacement = ac_nir_load_arg(b, s->args, s->args->draw_id);
+      break;
+   case nir_intrinsic_load_view_index:
+      replacement = ac_nir_load_arg(b, s->args, s->args->view_index);
+      break;
    default:
       return false;
    }
diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp
index 3d34c109510..af674872de2 100644
--- a/src/amd/compiler/aco_instruction_selection.cpp
+++ b/src/amd/compiler/aco_instruction_selection.cpp
@@ -8126,11 +8126,6 @@ visit_intrinsic(isel_context* ctx, nir_intrinsic_instr* instr)
       bld.copy(Definition(get_ssa_temp(ctx, &instr->def)), get_arg(ctx, ctx->args->front_face));
       break;
    }
-   case nir_intrinsic_load_view_index: {
-      Temp dst = get_ssa_temp(ctx, &instr->def);
-      bld.copy(Definition(dst), Operand(get_arg(ctx, ctx->args->view_index)));
-      break;
-   }
    case nir_intrinsic_load_frag_shading_rate:
       emit_load_frag_shading_rate(ctx, get_ssa_temp(ctx, &instr->def));
       break;
@@ -9009,26 +9004,11 @@ visit_intrinsic(isel_context* ctx, nir_intrinsic_instr* instr)
       bld.copy(Definition(dst), get_arg(ctx, ctx->args->vertex_id));
       break;
    }
-   case nir_intrinsic_load_first_vertex: {
-      Temp dst = get_ssa_temp(ctx, &instr->def);
-      bld.copy(Definition(dst), get_arg(ctx, ctx->args->base_vertex));
-      break;
-   }
-   case nir_intrinsic_load_base_instance: {
-      Temp dst = get_ssa_temp(ctx, &instr->def);
-      bld.copy(Definition(dst), get_arg(ctx, ctx->args->start_instance));
-      break;
-   }
    case nir_intrinsic_load_instance_id: {
       Temp dst = get_ssa_temp(ctx, &instr->def);
       bld.copy(Definition(dst), get_arg(ctx, ctx->args->instance_id));
       break;
    }
-   case nir_intrinsic_load_draw_id: {
-      Temp dst = get_ssa_temp(ctx, &instr->def);
-      bld.copy(Definition(dst), get_arg(ctx, ctx->args->draw_id));
-      break;
-   }
    case nir_intrinsic_load_invocation_id: {
       Temp dst = get_ssa_temp(ctx, &instr->def);
 
diff --git a/src/amd/compiler/aco_instruction_selection_setup.cpp b/src/amd/compiler/aco_instruction_selection_setup.cpp
index 6aa0b92fb90..eb6111a94be 100644
--- a/src/amd/compiler/aco_instruction_selection_setup.cpp
+++ b/src/amd/compiler/aco_instruction_selection_setup.cpp
@@ -529,8 +529,6 @@ init_context(isel_context* ctx, nir_shader* shader)
                case nir_intrinsic_load_sbt_base_amd:
                case nir_intrinsic_load_subgroup_id:
                case nir_intrinsic_load_num_subgroups:
-               case nir_intrinsic_load_first_vertex:
-               case nir_intrinsic_load_base_instance:
                case nir_intrinsic_vote_all:
                case nir_intrinsic_vote_any:
                case nir_intrinsic_read_first_invocation:
@@ -623,12 +621,7 @@ init_context(isel_context* ctx, nir_shader* shader)
                case nir_intrinsic_ddx_fine:
                case nir_intrinsic_ddy_fine:
                case nir_intrinsic_ddx_coarse:
-               case nir_intrinsic_ddy_coarse:
-                  type = RegType::vgpr;
-                  break;
-               case nir_intrinsic_load_view_index:
-                  type = ctx->stage == fragment_fs ? RegType::vgpr : RegType::sgpr;
-                  break;
+               case nir_intrinsic_ddy_coarse: type = RegType::vgpr; break;
                default:
                   for (unsigned i = 0; i < nir_intrinsic_infos[intrinsic->intrinsic].num_srcs;
                        i++) {
diff --git a/src/amd/llvm/ac_nir_to_llvm.c b/src/amd/llvm/ac_nir_to_llvm.c
index f88edc2d069..08e296c8207 100644
--- a/src/amd/llvm/ac_nir_to_llvm.c
+++ b/src/amd/llvm/ac_nir_to_llvm.c
@@ -2945,8 +2945,6 @@ static bool visit_intrinsic(struct ac_nir_context *ctx, nir_intrinsic_instr *ins
          unreachable("invalid stage");
       }
       break;
-   case nir_intrinsic_load_base_vertex:
-   case nir_intrinsic_load_first_vertex:
    case nir_intrinsic_load_ring_attr_amd:
    case nir_intrinsic_load_lds_ngg_scratch_base_amd:
    case nir_intrinsic_load_lds_ngg_gs_out_vertex_base_amd:
@@ -2955,15 +2953,6 @@ static bool visit_intrinsic(struct ac_nir_context *ctx, nir_intrinsic_instr *ins
    case nir_intrinsic_load_vertex_id_zero_base:
       result = ctx->abi->vertex_id_replaced ? ctx->abi->vertex_id_replaced : ctx->abi->vertex_id;
       break;
-   case nir_intrinsic_load_base_instance:
-      result = ac_get_arg(&ctx->ac, ctx->args->start_instance);
-      break;
-   case nir_intrinsic_load_draw_id:
-      result = ac_get_arg(&ctx->ac, ctx->args->draw_id);
-      break;
-   case nir_intrinsic_load_view_index:
-      result = ac_get_arg(&ctx->ac, ctx->args->view_index);
-      break;
    case nir_intrinsic_load_invocation_id:
       assert(ctx->stage == MESA_SHADER_TESS_CTRL || ctx->stage == MESA_SHADER_GEOMETRY);
       if (ctx->stage == MESA_SHADER_TESS_CTRL) {
diff --git a/src/amd/vulkan/radv_nir_to_llvm.c b/src/amd/vulkan/radv_nir_to_llvm.c
index 91868b5bef6..7c10f26b896 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -215,18 +215,6 @@ declare_esgs_ring(struct radv_shader_context *ctx)
    LLVMSetAlignment(esgs_ring, 64 * 1024);
 }
 
-static LLVMValueRef
-radv_intrinsic_load(struct ac_shader_abi *abi, nir_intrinsic_instr *intrin)
-{
-   switch (intrin->intrinsic) {
-   case nir_intrinsic_load_base_vertex:
-   case nir_intrinsic_load_first_vertex:
-      return radv_load_base_vertex(abi, intrin->intrinsic == nir_intrinsic_load_base_vertex);
-   default:
-      return NULL;
-   }
-}
-
 static LLVMModuleRef
 ac_translate_nir_to_llvm(struct ac_llvm_compiler *ac_llvm, const struct radv_nir_compiler_options *options,
                          const struct radv_shader_info *info, struct nir_shader *const *shaders, int shader_count,
@@ -280,7 +268,6 @@ ac_translate_nir_to_llvm(struct ac_llvm_compiler *ac_llvm, const struct radv_nir
 
    create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2);
 
-   ctx.abi.intrinsic_load = radv_intrinsic_load;
    ctx.abi.load_ubo = radv_load_ubo;
    ctx.abi.load_ssbo = radv_load_ssbo;
    ctx.abi.load_sampler_desc = radv_get_sampler_desc;
diff --git a/src/gallium/drivers/radeonsi/si_nir_lower_abi.c b/src/gallium/drivers/radeonsi/si_nir_lower_abi.c
index 0608b7c9ee3..0a43cd223cc 100644
--- a/src/gallium/drivers/radeonsi/si_nir_lower_abi.c
+++ b/src/gallium/drivers/radeonsi/si_nir_lower_abi.c
@@ -294,9 +294,6 @@ static bool lower_intrinsic(nir_builder *b, nir_instr *instr, struct lower_abi_s
    nir_def *replacement = NULL;
 
    switch (intrin->intrinsic) {
-   case nir_intrinsic_load_first_vertex:
-      replacement = ac_nir_load_arg(b, &args->ac, args->ac.base_vertex);
-      break;
    case nir_intrinsic_load_base_vertex: {
       nir_def *indexed = GET_FIELD_NIR(VS_STATE_INDEXED);
       indexed = nir_i2b(b, indexed);