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nv50/nir: align tlsspace to 0x10

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nvc0 aligns to 0x10 in setting up its rogram header, but nv50 TLS
allocation expects the incoming value to be aligned already (like TGSI
always did).  Avoids regression in
KHR-GL33.shaders.arrays.declaration.dynamic_expression_array_access_* with
the nir backend.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15949>
This commit is contained in:
Karol Herbst
2022-04-25 22:21:16 +02:00
committed by Marge Bot
parent c228cb3889
commit d1ff453a0d
1 changed files with 1 additions and 1 deletions
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src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
+1 -1
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@@ -1301,7 +1301,7 @@ Converter::storeTo(nir_intrinsic_instr *insn, DataFile file, operation op,
bool
Converter::parseNIR()
{
info_out->bin.tlsSpace = nir->scratch_size;
info_out->bin.tlsSpace = ALIGN(nir->scratch_size, 0x10);
info_out->io.clipDistances = nir->info.clip_distance_array_size;
info_out->io.cullDistances = nir->info.cull_distance_array_size;
info_out->io.layer_viewport_relative = nir->info.layer_viewport_relative;