diff --git a/src/freedreno/registers/adreno/a5xx.xml b/src/freedreno/registers/adreno/a5xx.xml
index b85f1954024..2b0b31a1f21 100644
--- a/src/freedreno/registers/adreno/a5xx.xml
+++ b/src/freedreno/registers/adreno/a5xx.xml
@@ -2815,8 +2815,6 @@ bit 7 for RECTLIST (clear) when z32s8 (used for clear of depth32?  not set
 
 0x2184 0x9 for copy, 0x1 for blit (maybe bitmask of enabled src/dst???)
  -->
-	<reg32 offset="0x2100" name="UNKNOWN_2100"/>
-	<reg32 offset="0x2180" name="UNKNOWN_2180"/>
 	<reg32 offset="0x2184" name="UNKNOWN_2184"/>
 </domain>
 
diff --git a/src/gallium/drivers/freedreno/a5xx/fd5_blitter.c b/src/gallium/drivers/freedreno/a5xx/fd5_blitter.c
index fe2bba5ef2b..7cf61de809f 100644
--- a/src/gallium/drivers/freedreno/a5xx/fd5_blitter.c
+++ b/src/gallium/drivers/freedreno/a5xx/fd5_blitter.c
@@ -156,11 +156,11 @@ emit_setup(struct fd_ringbuffer *ring)
    OUT_PKT4(ring, REG_A5XX_RB_RENDER_CNTL, 1);
    OUT_RING(ring, 0x00000008);
 
-   OUT_PKT4(ring, REG_A5XX_UNKNOWN_2100, 1);
-   OUT_RING(ring, 0x86000000); /* UNKNOWN_2100 */
+   OUT_PKT4(ring, REG_A5XX_RB_2D_BLIT_CNTL, 1);
+   OUT_RING(ring, 0x86000000); /* RB_2D_BLIT_CNTL */
 
-   OUT_PKT4(ring, REG_A5XX_UNKNOWN_2180, 1);
-   OUT_RING(ring, 0x86000000); /* UNKNOWN_2180 */
+   OUT_PKT4(ring, REG_A5XX_GRAS_2D_BLIT_CNTL, 1);
+   OUT_RING(ring, 0x86000000); /* 2D_BLIT_CNTL */
 
    OUT_PKT4(ring, REG_A5XX_UNKNOWN_2184, 1);
    OUT_RING(ring, 0x00000009); /* UNKNOWN_2184 */