From d06c0a370e05a58eac5e842730691940c8786dc9 Mon Sep 17 00:00:00 2001 From: Caio Oliveira Date: Fri, 22 Aug 2025 00:30:40 -0700 Subject: [PATCH] brw: Add brw_urb_inst Reviewed-by: Lionel Landwerlin Reviewed-by: Kenneth Graunke Part-of: --- src/intel/compiler/brw_builder.h | 8 +- src/intel/compiler/brw_compile_gs.cpp | 14 +- src/intel/compiler/brw_compile_tcs.cpp | 6 +- src/intel/compiler/brw_eu_defines.h | 1 - src/intel/compiler/brw_from_nir.cpp | 151 +++++++++--------- src/intel/compiler/brw_inst.cpp | 9 +- src/intel/compiler/brw_inst.h | 10 +- .../compiler/brw_lower_logical_sends.cpp | 100 ++++++------ src/intel/compiler/brw_opt_cse.cpp | 28 +++- src/intel/compiler/brw_print.cpp | 2 +- src/intel/compiler/brw_shader.cpp | 26 +-- 11 files changed, 194 insertions(+), 161 deletions(-) diff --git a/src/intel/compiler/brw_builder.h b/src/intel/compiler/brw_builder.h index 3d48b6fd2e0..a28c237a58e 100644 --- a/src/intel/compiler/brw_builder.h +++ b/src/intel/compiler/brw_builder.h @@ -638,18 +638,18 @@ public: return emit(SHADER_OPCODE_SEND, SEND_NUM_SRCS)->as_send(); } - brw_inst * + brw_urb_inst * URB_WRITE(const brw_reg srcs[], unsigned num_srcs) const { assert(num_srcs == URB_LOGICAL_NUM_SRCS); - return emit(SHADER_OPCODE_URB_WRITE_LOGICAL, reg_undef, srcs, num_srcs); + return emit(SHADER_OPCODE_URB_WRITE_LOGICAL, reg_undef, srcs, num_srcs)->as_urb(); } - brw_inst * + brw_urb_inst * URB_READ(const brw_reg &dst, const brw_reg srcs[], unsigned num_srcs) const { assert(num_srcs == URB_LOGICAL_NUM_SRCS); - return emit(SHADER_OPCODE_URB_READ_LOGICAL, dst, srcs, num_srcs); + return emit(SHADER_OPCODE_URB_READ_LOGICAL, dst, srcs, num_srcs)->as_urb(); } brw_inst * diff --git a/src/intel/compiler/brw_compile_gs.cpp b/src/intel/compiler/brw_compile_gs.cpp index b31bb048cfb..0e7853119c2 100644 --- a/src/intel/compiler/brw_compile_gs.cpp +++ b/src/intel/compiler/brw_compile_gs.cpp @@ -41,7 +41,7 @@ brw_emit_gs_thread_end(brw_shader &s) } const brw_builder abld = brw_builder(&s).annotate("thread end"); - brw_inst *inst; + brw_urb_inst *urb; if (gs_prog_data->static_vertex_count != -1) { /* Try and tag the last URB write with EOT instead of emitting a whole @@ -52,17 +52,17 @@ brw_emit_gs_thread_end(brw_shader &s) brw_reg srcs[URB_LOGICAL_NUM_SRCS]; srcs[URB_LOGICAL_SRC_HANDLE] = s.gs_payload().urb_handles; - srcs[URB_LOGICAL_SRC_COMPONENTS] = brw_imm_ud(0); - inst = abld.URB_WRITE(srcs, ARRAY_SIZE(srcs)); + urb = abld.URB_WRITE(srcs, ARRAY_SIZE(srcs)); + urb->components = 0; } else { brw_reg srcs[URB_LOGICAL_NUM_SRCS]; srcs[URB_LOGICAL_SRC_HANDLE] = s.gs_payload().urb_handles; srcs[URB_LOGICAL_SRC_DATA] = s.final_gs_vertex_count; - srcs[URB_LOGICAL_SRC_COMPONENTS] = brw_imm_ud(1); - inst = abld.URB_WRITE(srcs, ARRAY_SIZE(srcs)); + urb = abld.URB_WRITE(srcs, ARRAY_SIZE(srcs)); + urb->components = 1; } - inst->eot = true; - inst->offset = 0; + urb->eot = true; + urb->offset = 0; } static void diff --git a/src/intel/compiler/brw_compile_tcs.cpp b/src/intel/compiler/brw_compile_tcs.cpp index f71cd3b56f6..9f2490a8977 100644 --- a/src/intel/compiler/brw_compile_tcs.cpp +++ b/src/intel/compiler/brw_compile_tcs.cpp @@ -108,9 +108,9 @@ brw_emit_tcs_thread_end(brw_shader &s) srcs[URB_LOGICAL_SRC_HANDLE] = s.tcs_payload().patch_urb_output; srcs[URB_LOGICAL_SRC_CHANNEL_MASK] = brw_imm_ud(WRITEMASK_X); srcs[URB_LOGICAL_SRC_DATA] = brw_imm_ud(0); - srcs[URB_LOGICAL_SRC_COMPONENTS] = brw_imm_ud(1); - brw_inst *inst = bld.URB_WRITE(srcs, ARRAY_SIZE(srcs)); - inst->eot = true; + brw_urb_inst *urb = bld.URB_WRITE(srcs, ARRAY_SIZE(srcs)); + urb->eot = true; + urb->components = 1; } static void diff --git a/src/intel/compiler/brw_eu_defines.h b/src/intel/compiler/brw_eu_defines.h index 772eeac15c6..2aa39b617ea 100644 --- a/src/intel/compiler/brw_eu_defines.h +++ b/src/intel/compiler/brw_eu_defines.h @@ -733,7 +733,6 @@ enum urb_logical_srcs { URB_LOGICAL_SRC_CHANNEL_MASK, /** Data to be written. BAD_FILE for reads. */ URB_LOGICAL_SRC_DATA, - URB_LOGICAL_SRC_COMPONENTS, URB_LOGICAL_NUM_SRCS }; diff --git a/src/intel/compiler/brw_from_nir.cpp b/src/intel/compiler/brw_from_nir.cpp index 05df4de7e4f..c260e61ac99 100644 --- a/src/intel/compiler/brw_from_nir.cpp +++ b/src/intel/compiler/brw_from_nir.cpp @@ -2526,10 +2526,10 @@ brw_shader::emit_gs_control_data_bits(const brw_reg &vertex_count) srcs[URB_LOGICAL_SRC_PER_SLOT_OFFSETS] = per_slot_offset; srcs[URB_LOGICAL_SRC_CHANNEL_MASK] = channel_mask; srcs[URB_LOGICAL_SRC_DATA] = bld.vgrf(BRW_TYPE_F, length); - srcs[URB_LOGICAL_SRC_COMPONENTS] = brw_imm_ud(length); abld.LOAD_PAYLOAD(srcs[URB_LOGICAL_SRC_DATA], sources, length, 0); - brw_inst *inst = abld.URB_WRITE(srcs, ARRAY_SIZE(srcs)); + brw_urb_inst *urb = abld.URB_WRITE(srcs, ARRAY_SIZE(srcs)); + urb->components = length; /* We need to increment Global Offset by 256-bits to make room for * Broadwell's extra "Vertex Count" payload at the beginning of the @@ -2537,7 +2537,7 @@ brw_shader::emit_gs_control_data_bits(const brw_reg &vertex_count) * in 128-bit units, so we must set it to 2. */ if (gs_prog_data->static_vertex_count == -1) - inst->offset = 2; + urb->offset = 2; } static void @@ -2790,7 +2790,7 @@ emit_gs_input_load(nir_to_brw_state &ntb, const brw_reg &dst, } } - brw_inst *inst; + brw_urb_inst *urb; brw_reg indirect_offset = get_nir_src(ntb, offset_src, 0); if (nir_src_is_const(offset_src)) { @@ -2801,17 +2801,17 @@ emit_gs_input_load(nir_to_brw_state &ntb, const brw_reg &dst, if (first_component != 0) { unsigned read_components = num_components + first_component; brw_reg tmp = bld.vgrf(dst.type, read_components); - inst = bld.URB_READ(tmp, srcs, ARRAY_SIZE(srcs)); - inst->size_written = read_components * - tmp.component_size(inst->exec_size); + urb = bld.URB_READ(tmp, srcs, ARRAY_SIZE(srcs)); + urb->size_written = read_components * + tmp.component_size(urb->exec_size); brw_combine_with_vec(bld, dst, offset(tmp, bld, first_component), num_components); } else { - inst = bld.URB_READ(dst, srcs, ARRAY_SIZE(srcs)); - inst->size_written = num_components * - dst.component_size(inst->exec_size); + urb = bld.URB_READ(dst, srcs, ARRAY_SIZE(srcs)); + urb->size_written = num_components * + dst.component_size(urb->exec_size); } - inst->offset = base_offset + nir_src_as_uint(offset_src); + urb->offset = base_offset + nir_src_as_uint(offset_src); } else { /* Indirect indexing - use per-slot offsets as well. */ unsigned read_components = num_components + first_component; @@ -2826,17 +2826,17 @@ emit_gs_input_load(nir_to_brw_state &ntb, const brw_reg &dst, srcs[URB_LOGICAL_SRC_PER_SLOT_OFFSETS] = indirect_offset; if (first_component != 0) { - inst = bld.URB_READ(tmp, srcs, ARRAY_SIZE(srcs)); - inst->size_written = read_components * - tmp.component_size(inst->exec_size); + urb = bld.URB_READ(tmp, srcs, ARRAY_SIZE(srcs)); + urb->size_written = read_components * + tmp.component_size(urb->exec_size); brw_combine_with_vec(bld, dst, offset(tmp, bld, first_component), num_components); } else { - inst = bld.URB_READ(dst, srcs, ARRAY_SIZE(srcs)); - inst->size_written = num_components * - dst.component_size(inst->exec_size); + urb = bld.URB_READ(dst, srcs, ARRAY_SIZE(srcs)); + urb->size_written = num_components * + dst.component_size(urb->exec_size); } - inst->offset = base_offset; + urb->offset = base_offset; } } @@ -3142,7 +3142,7 @@ brw_from_nir_emit_tcs_intrinsic(nir_to_brw_state &ntb, assert(instr->def.bit_size == 32); brw_reg indirect_offset = get_indirect_offset(ntb, instr); unsigned imm_offset = nir_intrinsic_base(instr); - brw_inst *inst; + brw_urb_inst *urb; const bool multi_patch = vue_prog_data->dispatch_mode == INTEL_DISPATCH_MODE_TCS_MULTI_PATCH; @@ -3166,13 +3166,13 @@ brw_from_nir_emit_tcs_intrinsic(nir_to_brw_state &ntb, if (first_component != 0) { unsigned read_components = num_components + first_component; brw_reg tmp = bld.vgrf(dst.type, read_components); - inst = bld.URB_READ(tmp, srcs, ARRAY_SIZE(srcs)); + urb = bld.URB_READ(tmp, srcs, ARRAY_SIZE(srcs)); brw_combine_with_vec(bld, dst, offset(tmp, bld, first_component), num_components); } else { - inst = bld.URB_READ(dst, srcs, ARRAY_SIZE(srcs)); + urb = bld.URB_READ(dst, srcs, ARRAY_SIZE(srcs)); } - inst->offset = imm_offset; + urb->offset = imm_offset; } else { /* Indirect indexing - use per-slot offsets as well. */ srcs[URB_LOGICAL_SRC_PER_SLOT_OFFSETS] = indirect_offset; @@ -3180,26 +3180,26 @@ brw_from_nir_emit_tcs_intrinsic(nir_to_brw_state &ntb, if (first_component != 0) { unsigned read_components = num_components + first_component; brw_reg tmp = bld.vgrf(dst.type, read_components); - inst = bld.URB_READ(tmp, srcs, ARRAY_SIZE(srcs)); + urb = bld.URB_READ(tmp, srcs, ARRAY_SIZE(srcs)); brw_combine_with_vec(bld, dst, offset(tmp, bld, first_component), num_components); } else { - inst = bld.URB_READ(dst, srcs, ARRAY_SIZE(srcs)); + urb = bld.URB_READ(dst, srcs, ARRAY_SIZE(srcs)); } - inst->offset = imm_offset; + urb->offset = imm_offset; } - inst->size_written = (num_components + first_component) * - inst->dst.component_size(inst->exec_size); + urb->size_written = (num_components + first_component) * + urb->dst.component_size(urb->exec_size); /* Copy the temporary to the destination to deal with writemasking. * * Also attempt to deal with gl_PointSize being in the .w component. */ - if (inst->offset == 0 && indirect_offset.file == BAD_FILE) { + if (urb->offset == 0 && indirect_offset.file == BAD_FILE) { assert(brw_type_size_bytes(dst.type) == 4); - inst->dst = bld.vgrf(dst.type, 4); - inst->size_written = 4 * REG_SIZE * reg_unit(devinfo); - bld.MOV(dst, offset(inst->dst, bld, 3)); + urb->dst = bld.vgrf(dst.type, 4); + urb->size_written = 4 * REG_SIZE * reg_unit(devinfo); + bld.MOV(dst, offset(urb->dst, bld, 3)); } break; } @@ -3211,7 +3211,7 @@ brw_from_nir_emit_tcs_intrinsic(nir_to_brw_state &ntb, unsigned imm_offset = nir_intrinsic_base(instr); unsigned first_component = nir_intrinsic_component(instr); - brw_inst *inst; + brw_urb_inst *urb; if (indirect_offset.file == BAD_FILE) { /* This MOV replicates the output handle to all enabled channels * is SINGLE_PATCH mode. @@ -3226,15 +3226,15 @@ brw_from_nir_emit_tcs_intrinsic(nir_to_brw_state &ntb, unsigned read_components = instr->num_components + first_component; brw_reg tmp = bld.vgrf(dst.type, read_components); - inst = bld.URB_READ(tmp, srcs, ARRAY_SIZE(srcs)); - inst->size_written = read_components * REG_SIZE * reg_unit(devinfo); + urb = bld.URB_READ(tmp, srcs, ARRAY_SIZE(srcs)); + urb->size_written = read_components * REG_SIZE * reg_unit(devinfo); brw_combine_with_vec(bld, dst, offset(tmp, bld, first_component), instr->num_components); } else { - inst = bld.URB_READ(dst, srcs, ARRAY_SIZE(srcs)); - inst->size_written = instr->num_components * REG_SIZE * reg_unit(devinfo); + urb = bld.URB_READ(dst, srcs, ARRAY_SIZE(srcs)); + urb->size_written = instr->num_components * REG_SIZE * reg_unit(devinfo); } - inst->offset = imm_offset; + urb->offset = imm_offset; } } else { /* Indirect indexing - use per-slot offsets as well. */ @@ -3246,15 +3246,15 @@ brw_from_nir_emit_tcs_intrinsic(nir_to_brw_state &ntb, unsigned read_components = instr->num_components + first_component; brw_reg tmp = bld.vgrf(dst.type, read_components); - inst = bld.URB_READ(tmp, srcs, ARRAY_SIZE(srcs)); - inst->size_written = read_components * REG_SIZE * reg_unit(devinfo); + urb = bld.URB_READ(tmp, srcs, ARRAY_SIZE(srcs)); + urb->size_written = read_components * REG_SIZE * reg_unit(devinfo); brw_combine_with_vec(bld, dst, offset(tmp, bld, first_component), instr->num_components); } else { - inst = bld.URB_READ(dst, srcs, ARRAY_SIZE(srcs)); - inst->size_written = instr->num_components * REG_SIZE * reg_unit(devinfo); + urb = bld.URB_READ(dst, srcs, ARRAY_SIZE(srcs)); + urb->size_written = instr->num_components * REG_SIZE * reg_unit(devinfo); } - inst->offset = imm_offset; + urb->offset = imm_offset; } break; } @@ -3301,11 +3301,11 @@ brw_from_nir_emit_tcs_intrinsic(nir_to_brw_state &ntb, srcs[URB_LOGICAL_SRC_PER_SLOT_OFFSETS] = indirect_offset; srcs[URB_LOGICAL_SRC_CHANNEL_MASK] = mask_reg; srcs[URB_LOGICAL_SRC_DATA] = bld.vgrf(BRW_TYPE_F, m); - srcs[URB_LOGICAL_SRC_COMPONENTS] = brw_imm_ud(m); bld.LOAD_PAYLOAD(srcs[URB_LOGICAL_SRC_DATA], sources, m, 0); - brw_inst *inst = bld.URB_WRITE(srcs, ARRAY_SIZE(srcs)); - inst->offset = imm_offset; + brw_urb_inst *urb = bld.URB_WRITE(srcs, ARRAY_SIZE(srcs)); + urb->offset = imm_offset; + urb->components = m; break; } @@ -3352,7 +3352,7 @@ brw_from_nir_emit_tes_intrinsic(nir_to_brw_state &ntb, unsigned imm_offset = nir_intrinsic_base(instr); unsigned first_component = nir_intrinsic_component(instr); - brw_inst *inst; + brw_urb_inst *urb; if (indirect_offset.file == BAD_FILE) { /* Arbitrarily only push up to 32 vec4 slots worth of data, * which is 16 registers (since each holds 2 vec4 slots). @@ -3379,15 +3379,15 @@ brw_from_nir_emit_tes_intrinsic(nir_to_brw_state &ntb, unsigned read_components = instr->num_components + first_component; brw_reg tmp = bld.vgrf(dest.type, read_components); - inst = bld.URB_READ(tmp, srcs, ARRAY_SIZE(srcs)); - inst->size_written = read_components * REG_SIZE * reg_unit(devinfo); + urb = bld.URB_READ(tmp, srcs, ARRAY_SIZE(srcs)); + urb->size_written = read_components * REG_SIZE * reg_unit(devinfo); brw_combine_with_vec(bld, dest, offset(tmp, bld, first_component), instr->num_components); } else { - inst = bld.URB_READ(dest, srcs, ARRAY_SIZE(srcs)); - inst->size_written = instr->num_components * REG_SIZE * reg_unit(devinfo); + urb = bld.URB_READ(dest, srcs, ARRAY_SIZE(srcs)); + urb->size_written = instr->num_components * REG_SIZE * reg_unit(devinfo); } - inst->offset = imm_offset; + urb->offset = imm_offset; } } else { /* Indirect indexing - use per-slot offsets as well. */ @@ -3406,15 +3406,15 @@ brw_from_nir_emit_tes_intrinsic(nir_to_brw_state &ntb, unsigned read_components = num_components + first_component; brw_reg tmp = bld.vgrf(dest.type, read_components); - inst = bld.URB_READ(tmp, srcs, ARRAY_SIZE(srcs)); + urb = bld.URB_READ(tmp, srcs, ARRAY_SIZE(srcs)); brw_combine_with_vec(bld, dest, offset(tmp, bld, first_component), num_components); } else { - inst = bld.URB_READ(dest, srcs, ARRAY_SIZE(srcs)); + urb = bld.URB_READ(dest, srcs, ARRAY_SIZE(srcs)); } - inst->offset = imm_offset; - inst->size_written = (num_components + first_component) * - inst->dst.component_size(inst->exec_size); + urb->offset = imm_offset; + urb->size_written = (num_components + first_component) * + urb->dst.component_size(urb->exec_size); } break; } @@ -5278,12 +5278,12 @@ emit_urb_direct_vec4_write(const brw_builder &bld, srcs[URB_LOGICAL_SRC_CHANNEL_MASK] = brw_imm_ud(mask); srcs[URB_LOGICAL_SRC_DATA] = retype(brw_allocate_vgrf_units(*bld.shader, length), BRW_TYPE_F); - srcs[URB_LOGICAL_SRC_COMPONENTS] = brw_imm_ud(length); bld8.LOAD_PAYLOAD(srcs[URB_LOGICAL_SRC_DATA], payload_srcs, length, 0); - brw_inst *inst = bld8.URB_WRITE(srcs, ARRAY_SIZE(srcs)); - inst->offset = urb_global_offset; - assert(inst->offset < 2048); + brw_urb_inst *urb = bld8.URB_WRITE(srcs, ARRAY_SIZE(srcs)); + urb->offset = urb_global_offset; + urb->components = length; + assert(urb->offset < 2048); } } @@ -5347,10 +5347,10 @@ emit_urb_direct_vec4_write_xe2(const brw_builder &bld, srcs[URB_LOGICAL_SRC_CHANNEL_MASK] = brw_imm_ud(mask); srcs[URB_LOGICAL_SRC_DATA] = retype(brw_allocate_vgrf_units(*bld.shader, comps * runit), BRW_TYPE_F); - srcs[URB_LOGICAL_SRC_COMPONENTS] = brw_imm_ud(comps); hbld.LOAD_PAYLOAD(srcs[URB_LOGICAL_SRC_DATA], payload_srcs, comps, 0); - hbld.URB_WRITE(srcs, ARRAY_SIZE(srcs)); + brw_urb_inst *urb = hbld.URB_WRITE(srcs, ARRAY_SIZE(srcs)); + urb->components = comps; } } @@ -5409,11 +5409,10 @@ emit_urb_indirect_vec4_write(const brw_builder &bld, srcs[URB_LOGICAL_SRC_CHANNEL_MASK] = brw_imm_ud(mask); srcs[URB_LOGICAL_SRC_DATA] = retype(brw_allocate_vgrf_units(*bld.shader, length), BRW_TYPE_F); - srcs[URB_LOGICAL_SRC_COMPONENTS] = brw_imm_ud(length); bld8.LOAD_PAYLOAD(srcs[URB_LOGICAL_SRC_DATA], payload_srcs, length, 0); - brw_inst *inst = bld8.URB_WRITE(srcs, ARRAY_SIZE(srcs)); - inst->offset = 0; + brw_urb_inst *urb = bld8.URB_WRITE(srcs, ARRAY_SIZE(srcs)); + urb->components = length; } } @@ -5479,10 +5478,10 @@ emit_urb_indirect_writes_xe2(const brw_builder &bld, nir_intrinsic_instr *instr, srcs[URB_LOGICAL_SRC_CHANNEL_MASK] = brw_imm_ud(mask); srcs[URB_LOGICAL_SRC_DATA] = retype(brw_allocate_vgrf_units(*bld.shader, comps * runit), BRW_TYPE_F); - srcs[URB_LOGICAL_SRC_COMPONENTS] = brw_imm_ud(comps); wbld.LOAD_PAYLOAD(srcs[URB_LOGICAL_SRC_DATA], payload_srcs, comps, 0); - wbld.URB_WRITE(srcs, ARRAY_SIZE(srcs)); + brw_urb_inst *urb = wbld.URB_WRITE(srcs, ARRAY_SIZE(srcs)); + urb->components = comps; } } @@ -5537,11 +5536,10 @@ emit_urb_indirect_writes(const brw_builder &bld, nir_intrinsic_instr *instr, srcs[URB_LOGICAL_SRC_CHANNEL_MASK] = mask; srcs[URB_LOGICAL_SRC_DATA] = retype(brw_allocate_vgrf_units(*bld.shader, length), BRW_TYPE_F); - srcs[URB_LOGICAL_SRC_COMPONENTS] = brw_imm_ud(length); bld8.LOAD_PAYLOAD(srcs[URB_LOGICAL_SRC_DATA], payload_srcs, length, 0); - brw_inst *inst = bld8.URB_WRITE(srcs, ARRAY_SIZE(srcs)); - inst->offset = 0; + brw_urb_inst *urb = bld8.URB_WRITE(srcs, ARRAY_SIZE(srcs)); + urb->components = length; } } } @@ -5574,10 +5572,10 @@ emit_urb_direct_reads(const brw_builder &bld, nir_intrinsic_instr *instr, brw_reg srcs[URB_LOGICAL_NUM_SRCS]; srcs[URB_LOGICAL_SRC_HANDLE] = urb_handle; - brw_inst *inst = ubld8.URB_READ(data, srcs, ARRAY_SIZE(srcs)); - inst->offset = urb_global_offset; - assert(inst->offset < 2048); - inst->size_written = num_regs * REG_SIZE; + brw_urb_inst *urb = ubld8.URB_READ(data, srcs, ARRAY_SIZE(srcs)); + urb->offset = urb_global_offset; + assert(urb->offset < 2048); + urb->size_written = num_regs * REG_SIZE; for (unsigned c = 0; c < comps; c++) { brw_reg dest_comp = offset(dest, bld, c); @@ -5671,9 +5669,8 @@ emit_urb_indirect_reads(const brw_builder &bld, nir_intrinsic_instr *instr, brw_reg data = bld8.vgrf(BRW_TYPE_UD, 4); - brw_inst *inst = bld8.URB_READ(data, srcs, ARRAY_SIZE(srcs)); - inst->offset = 0; - inst->size_written = 4 * REG_SIZE; + brw_urb_inst *urb = bld8.URB_READ(data, srcs, ARRAY_SIZE(srcs)); + urb->size_written = 4 * REG_SIZE; brw_reg dest_comp = offset(dest, bld, c); bld8.emit(SHADER_OPCODE_MOV_INDIRECT, diff --git a/src/intel/compiler/brw_inst.cpp b/src/intel/compiler/brw_inst.cpp index e666d850dc7..ec0464799c4 100644 --- a/src/intel/compiler/brw_inst.cpp +++ b/src/intel/compiler/brw_inst.cpp @@ -18,6 +18,7 @@ brw_inst_kind_size(brw_inst_kind kind) STATIC_ASSERT(sizeof(brw_send_inst) >= sizeof(brw_mem_inst)); STATIC_ASSERT(sizeof(brw_send_inst) >= sizeof(brw_dpas_inst)); STATIC_ASSERT(sizeof(brw_send_inst) >= sizeof(brw_load_payload_inst)); + STATIC_ASSERT(sizeof(brw_send_inst) >= sizeof(brw_urb_inst)); /* TODO: Temporarily here to ensure all instructions can be converted to * SEND. Once all new kinds are added, change so that BASE allocate only @@ -192,6 +193,10 @@ brw_inst_kind_for_opcode(enum opcode opcode) case SHADER_OPCODE_LOAD_PAYLOAD: return BRW_KIND_LOAD_PAYLOAD; + case SHADER_OPCODE_URB_READ_LOGICAL: + case SHADER_OPCODE_URB_WRITE_LOGICAL: + return BRW_KIND_URB; + default: return BRW_KIND_BASE; } @@ -512,10 +517,8 @@ brw_inst::components_read(unsigned i) const return (i == 0 ? 2 : 1); case SHADER_OPCODE_URB_WRITE_LOGICAL: - assert(src[URB_LOGICAL_SRC_COMPONENTS].file == IMM); - if (i == URB_LOGICAL_SRC_DATA) - return src[URB_LOGICAL_SRC_COMPONENTS].ud; + return as_urb()->components; else return 1; diff --git a/src/intel/compiler/brw_inst.h b/src/intel/compiler/brw_inst.h index 7c40a4c8be2..399da7084d5 100644 --- a/src/intel/compiler/brw_inst.h +++ b/src/intel/compiler/brw_inst.h @@ -46,6 +46,7 @@ enum ENUM_PACKED brw_inst_kind { BRW_KIND_MEM, BRW_KIND_DPAS, BRW_KIND_LOAD_PAYLOAD, + BRW_KIND_URB, }; brw_inst_kind brw_inst_kind_for_opcode(enum opcode opcode); @@ -76,6 +77,7 @@ struct brw_inst : brw_exec_node { KIND_HELPERS(as_mem, brw_mem_inst, BRW_KIND_MEM); KIND_HELPERS(as_dpas, brw_dpas_inst, BRW_KIND_DPAS); KIND_HELPERS(as_load_payload, brw_load_payload_inst, BRW_KIND_LOAD_PAYLOAD); + KIND_HELPERS(as_urb, brw_urb_inst, BRW_KIND_URB); #undef KIND_HELPERS @@ -170,7 +172,6 @@ struct brw_inst : brw_exec_node { */ uint8_t group; - uint32_t offset; /**< spill/unspill offset or texture offset bitfield */ uint16_t size_written; /**< Data written to the destination register in bytes. */ enum opcode opcode; /* BRW_OPCODE_* or FS_OPCODE_* */ @@ -232,6 +233,7 @@ struct brw_inst : brw_exec_node { struct brw_send_inst : brw_inst { uint32_t desc; uint32_t ex_desc; + uint32_t offset; uint8_t mlen; uint8_t ex_mlen; @@ -269,6 +271,7 @@ struct brw_send_inst : brw_inst { }; struct brw_tex_inst : brw_inst { + uint32_t offset; uint8_t coord_components; uint8_t grad_components; bool residency; @@ -303,6 +306,11 @@ struct brw_load_payload_inst : brw_inst { uint8_t header_size; }; +struct brw_urb_inst : brw_inst { + uint32_t offset; + uint8_t components; +}; + /** * Make the execution of \p inst dependent on the evaluation of a possibly * inverted predicate. diff --git a/src/intel/compiler/brw_lower_logical_sends.cpp b/src/intel/compiler/brw_lower_logical_sends.cpp index 32c1174c5e7..9e85bfbb0cc 100644 --- a/src/intel/compiler/brw_lower_logical_sends.cpp +++ b/src/intel/compiler/brw_lower_logical_sends.cpp @@ -38,25 +38,27 @@ brw_transform_inst_to_send(const brw_builder &bld, brw_inst *inst) } static void -lower_urb_read_logical_send(const brw_builder &bld, brw_inst *inst) +lower_urb_read_logical_send(const brw_builder &bld, brw_urb_inst *urb) { const intel_device_info *devinfo = bld.shader->devinfo; const bool per_slot_present = - inst->src[URB_LOGICAL_SRC_PER_SLOT_OFFSETS].file != BAD_FILE; + urb->src[URB_LOGICAL_SRC_PER_SLOT_OFFSETS].file != BAD_FILE; - assert(inst->size_written % REG_SIZE == 0); + assert(urb->size_written % REG_SIZE == 0); brw_reg payload_sources[2]; unsigned header_size = 0; - payload_sources[header_size++] = inst->src[URB_LOGICAL_SRC_HANDLE]; + payload_sources[header_size++] = urb->src[URB_LOGICAL_SRC_HANDLE]; if (per_slot_present) - payload_sources[header_size++] = inst->src[URB_LOGICAL_SRC_PER_SLOT_OFFSETS]; + payload_sources[header_size++] = urb->src[URB_LOGICAL_SRC_PER_SLOT_OFFSETS]; brw_reg payload = retype(brw_allocate_vgrf_units(*bld.shader, header_size), BRW_TYPE_F); bld.LOAD_PAYLOAD(payload, payload_sources, header_size, header_size); - brw_send_inst *send = brw_transform_inst_to_send(bld, inst); - inst = NULL; + const uint32_t offset = urb->offset; + + brw_send_inst *send = brw_transform_inst_to_send(bld, urb); + urb = NULL; send->header_size = header_size; @@ -65,7 +67,7 @@ lower_urb_read_logical_send(const brw_builder &bld, brw_inst *inst) GFX8_URB_OPCODE_SIMD8_READ, per_slot_present, false, - send->offset); + offset); send->mlen = header_size; send->ex_desc = 0; @@ -79,18 +81,18 @@ lower_urb_read_logical_send(const brw_builder &bld, brw_inst *inst) } static void -lower_urb_read_logical_send_xe2(const brw_builder &bld, brw_inst *inst) +lower_urb_read_logical_send_xe2(const brw_builder &bld, brw_urb_inst *urb) { const intel_device_info *devinfo = bld.shader->devinfo; assert(devinfo->has_lsc); - assert(inst->size_written % (REG_SIZE * reg_unit(devinfo)) == 0); + assert(urb->size_written % (REG_SIZE * reg_unit(devinfo)) == 0); /* Get the logical send arguments. */ - const brw_reg handle = inst->src[URB_LOGICAL_SRC_HANDLE]; + const brw_reg handle = urb->src[URB_LOGICAL_SRC_HANDLE]; /* Calculate the total number of components of the payload. */ - const unsigned dst_comps = inst->size_written / (REG_SIZE * reg_unit(devinfo)); + const unsigned dst_comps = urb->size_written / (REG_SIZE * reg_unit(devinfo)); brw_reg payload = bld.vgrf(BRW_TYPE_UD); @@ -99,18 +101,18 @@ lower_urb_read_logical_send_xe2(const brw_builder &bld, brw_inst *inst) /* The low 24-bits of the URB handle is a byte offset into the URB area. * Add the (OWord) offset of the write to this value. */ - if (inst->offset) { - bld.ADD(payload, payload, brw_imm_ud(inst->offset * 16)); - inst->offset = 0; + if (urb->offset) { + bld.ADD(payload, payload, brw_imm_ud(urb->offset * 16)); + urb->offset = 0; } - brw_reg offsets = inst->src[URB_LOGICAL_SRC_PER_SLOT_OFFSETS]; + brw_reg offsets = urb->src[URB_LOGICAL_SRC_PER_SLOT_OFFSETS]; if (offsets.file != BAD_FILE) { bld.ADD(payload, payload, offsets); } - brw_send_inst *send = brw_transform_inst_to_send(bld, inst); - inst = NULL; + brw_send_inst *send = brw_transform_inst_to_send(bld, urb); + urb = NULL; send->sfid = BRW_SFID_URB; @@ -136,43 +138,45 @@ lower_urb_read_logical_send_xe2(const brw_builder &bld, brw_inst *inst) } static void -lower_urb_write_logical_send(const brw_builder &bld, brw_inst *inst) +lower_urb_write_logical_send(const brw_builder &bld, brw_urb_inst *urb) { const intel_device_info *devinfo = bld.shader->devinfo; const bool per_slot_present = - inst->src[URB_LOGICAL_SRC_PER_SLOT_OFFSETS].file != BAD_FILE; + urb->src[URB_LOGICAL_SRC_PER_SLOT_OFFSETS].file != BAD_FILE; const bool channel_mask_present = - inst->src[URB_LOGICAL_SRC_CHANNEL_MASK].file != BAD_FILE; + urb->src[URB_LOGICAL_SRC_CHANNEL_MASK].file != BAD_FILE; const unsigned length = 1 + per_slot_present + channel_mask_present + - inst->components_read(URB_LOGICAL_SRC_DATA); + urb->components_read(URB_LOGICAL_SRC_DATA); brw_reg *payload_sources = new brw_reg[length]; brw_reg payload = retype(brw_allocate_vgrf_units(*bld.shader, length), BRW_TYPE_F); unsigned header_size = 0; - payload_sources[header_size++] = inst->src[URB_LOGICAL_SRC_HANDLE]; + payload_sources[header_size++] = urb->src[URB_LOGICAL_SRC_HANDLE]; if (per_slot_present) - payload_sources[header_size++] = inst->src[URB_LOGICAL_SRC_PER_SLOT_OFFSETS]; + payload_sources[header_size++] = urb->src[URB_LOGICAL_SRC_PER_SLOT_OFFSETS]; if (channel_mask_present) { payload_sources[header_size++] = - inst->src[URB_LOGICAL_SRC_CHANNEL_MASK].file == IMM ? - brw_imm_ud(inst->src[URB_LOGICAL_SRC_CHANNEL_MASK].ud << 16) : - bld.SHL(retype(inst->src[URB_LOGICAL_SRC_CHANNEL_MASK], BRW_TYPE_UD), + urb->src[URB_LOGICAL_SRC_CHANNEL_MASK].file == IMM ? + brw_imm_ud(urb->src[URB_LOGICAL_SRC_CHANNEL_MASK].ud << 16) : + bld.SHL(retype(urb->src[URB_LOGICAL_SRC_CHANNEL_MASK], BRW_TYPE_UD), brw_imm_ud(16)); } for (unsigned i = header_size, j = 0; i < length; i++, j++) - payload_sources[i] = offset(inst->src[URB_LOGICAL_SRC_DATA], bld, j); + payload_sources[i] = offset(urb->src[URB_LOGICAL_SRC_DATA], bld, j); bld.LOAD_PAYLOAD(payload, payload_sources, length, header_size); delete [] payload_sources; - brw_send_inst *send = brw_transform_inst_to_send(bld, inst); - inst = NULL; + const uint32_t offset = urb->offset; + + brw_send_inst *send = brw_transform_inst_to_send(bld, urb); + urb = NULL; send->header_size = header_size; send->dst = brw_null_reg(); @@ -182,7 +186,7 @@ lower_urb_write_logical_send(const brw_builder &bld, brw_inst *inst) GFX8_URB_OPCODE_SIMD8_WRITE, per_slot_present, channel_mask_present, - send->offset); + offset); send->mlen = length; send->ex_desc = 0; @@ -196,19 +200,19 @@ lower_urb_write_logical_send(const brw_builder &bld, brw_inst *inst) } static void -lower_urb_write_logical_send_xe2(const brw_builder &bld, brw_inst *inst) +lower_urb_write_logical_send_xe2(const brw_builder &bld, brw_urb_inst *urb) { const intel_device_info *devinfo = bld.shader->devinfo; assert(devinfo->has_lsc); /* Get the logical send arguments. */ - const brw_reg handle = inst->src[URB_LOGICAL_SRC_HANDLE]; - const brw_reg src = inst->components_read(URB_LOGICAL_SRC_DATA) ? - inst->src[URB_LOGICAL_SRC_DATA] : brw_reg(brw_imm_ud(0)); + const brw_reg handle = urb->src[URB_LOGICAL_SRC_HANDLE]; + const brw_reg src = urb->components_read(URB_LOGICAL_SRC_DATA) ? + urb->src[URB_LOGICAL_SRC_DATA] : brw_reg(brw_imm_ud(0)); assert(brw_type_size_bytes(src.type) == 4); /* Calculate the total number of components of the payload. */ - const unsigned src_comps = MAX2(1, inst->components_read(URB_LOGICAL_SRC_DATA)); + const unsigned src_comps = MAX2(1, urb->components_read(URB_LOGICAL_SRC_DATA)); const unsigned src_sz = brw_type_size_bytes(src.type); brw_reg payload = bld.vgrf(BRW_TYPE_UD); @@ -218,19 +222,19 @@ lower_urb_write_logical_send_xe2(const brw_builder &bld, brw_inst *inst) /* The low 24-bits of the URB handle is a byte offset into the URB area. * Add the (OWord) offset of the write to this value. */ - if (inst->offset) { - bld.ADD(payload, payload, brw_imm_ud(inst->offset * 16)); - inst->offset = 0; + if (urb->offset) { + bld.ADD(payload, payload, brw_imm_ud(urb->offset * 16)); + urb->offset = 0; } - brw_reg offsets = inst->src[URB_LOGICAL_SRC_PER_SLOT_OFFSETS]; + brw_reg offsets = urb->src[URB_LOGICAL_SRC_PER_SLOT_OFFSETS]; if (offsets.file != BAD_FILE) { bld.ADD(payload, payload, offsets); } unsigned num_channels_or_cmask = src_comps; - const brw_reg cmask = inst->src[URB_LOGICAL_SRC_CHANNEL_MASK]; + const brw_reg cmask = urb->src[URB_LOGICAL_SRC_CHANNEL_MASK]; brw_reg desc = brw_imm_ud(0); if (cmask.file == IMM) { assert(cmask.type == BRW_TYPE_UD); @@ -242,10 +246,10 @@ lower_urb_write_logical_send_xe2(const brw_builder &bld, brw_inst *inst) } brw_reg payload2 = bld.move_to_vgrf(src, src_comps); - const unsigned ex_mlen = (src_comps * src_sz * inst->exec_size) / REG_SIZE; + const unsigned ex_mlen = (src_comps * src_sz * urb->exec_size) / REG_SIZE; - brw_send_inst *send = brw_transform_inst_to_send(bld, inst); - inst = NULL; + brw_send_inst *send = brw_transform_inst_to_send(bld, urb); + urb = NULL; send->sfid = BRW_SFID_URB; @@ -2687,16 +2691,16 @@ brw_lower_logical_sends(brw_shader &s) case SHADER_OPCODE_URB_READ_LOGICAL: if (devinfo->ver < 20) - lower_urb_read_logical_send(ibld, inst); + lower_urb_read_logical_send(ibld, inst->as_urb()); else - lower_urb_read_logical_send_xe2(ibld, inst); + lower_urb_read_logical_send_xe2(ibld, inst->as_urb()); break; case SHADER_OPCODE_URB_WRITE_LOGICAL: if (devinfo->ver < 20) - lower_urb_write_logical_send(ibld, inst); + lower_urb_write_logical_send(ibld, inst->as_urb()); else - lower_urb_write_logical_send_xe2(ibld, inst); + lower_urb_write_logical_send_xe2(ibld, inst->as_urb()); break; diff --git a/src/intel/compiler/brw_opt_cse.cpp b/src/intel/compiler/brw_opt_cse.cpp index 5473df8b401..8930301dea3 100644 --- a/src/intel/compiler/brw_opt_cse.cpp +++ b/src/intel/compiler/brw_opt_cse.cpp @@ -249,13 +249,15 @@ send_inst_match(brw_send_inst *a, brw_send_inst *b) a->header_size == b->header_size && a->desc == b->desc && a->ex_desc == b->ex_desc && + a->offset == b->offset && a->send_bits == b->send_bits; } static bool tex_inst_match(brw_tex_inst *a, brw_tex_inst *b) { - return a->coord_components == b->coord_components && + return a->offset == b->offset && + a->coord_components == b->coord_components && a->grad_components == b->grad_components && a->residency == b->residency; } @@ -287,6 +289,13 @@ load_payload_inst_match(brw_load_payload_inst *a, brw_load_payload_inst *b) return a->header_size == b->header_size; } +static bool +urb_inst_match(brw_urb_inst *a, brw_urb_inst *b) +{ + return a->offset == b->offset && + a->components == b->components; +} + static bool instructions_match(brw_inst *a, brw_inst *b, bool *negate) { @@ -299,12 +308,12 @@ instructions_match(brw_inst *a, brw_inst *b, bool *negate) (a->kind != BRW_KIND_DPAS || dpas_inst_match(a->as_dpas(), b->as_dpas())) && (a->kind != BRW_KIND_LOAD_PAYLOAD || load_payload_inst_match(a->as_load_payload(), b->as_load_payload())) && + (a->kind != BRW_KIND_URB || urb_inst_match(a->as_urb(), b->as_urb())) && a->exec_size == b->exec_size && a->group == b->group && a->predicate == b->predicate && a->conditional_mod == b->conditional_mod && a->dst.type == b->dst.type && - a->offset == b->offset && a->size_written == b->size_written && a->sources == b->sources && a->bits == b->bits && @@ -352,7 +361,6 @@ hash_inst(const void *v) inst->predicate, }; const uint32_t u32data[] = { - inst->offset, inst->size_written, inst->opcode, inst->bits, @@ -376,6 +384,7 @@ hash_inst(const void *v) const uint32_t send_u32data[] = { send->desc, send->ex_desc, + send->offset, }; hash = HASH(hash, send_u8data); hash = HASH(hash, send_u32data); @@ -432,6 +441,19 @@ hash_inst(const void *v) break; } + case BRW_KIND_URB: { + const brw_urb_inst *urb = inst->as_urb(); + const uint8_t urb_u8data[] = { + urb->components, + }; + const uint32_t urb_u32data[] = { + urb->offset, + }; + hash = HASH(hash, urb_u8data); + hash = HASH(hash, urb_u32data); + break; + } + case BRW_KIND_BASE: /* Nothing else to do. */ break; diff --git a/src/intel/compiler/brw_print.cpp b/src/intel/compiler/brw_print.cpp index 7dec8aaa213..688b993f5bf 100644 --- a/src/intel/compiler/brw_print.cpp +++ b/src/intel/compiler/brw_print.cpp @@ -663,7 +663,7 @@ brw_print_instruction(const brw_shader &s, const brw_inst *inst, FILE *file, con fprintf(file, "ExDesc 0x%08x ", send->ex_desc); if (send && send->ex_desc_imm) - fprintf(file, "ExDescImmInst 0x%08x ", inst->offset); + fprintf(file, "ExDescImmInst 0x%08x ", send->offset); if (inst->sched.regdist || inst->sched.mode) { fprintf(file, "{ "); diff --git a/src/intel/compiler/brw_shader.cpp b/src/intel/compiler/brw_shader.cpp index 14ebfc39206..172e4a28301 100644 --- a/src/intel/compiler/brw_shader.cpp +++ b/src/intel/compiler/brw_shader.cpp @@ -240,18 +240,18 @@ brw_shader::emit_urb_writes(const brw_reg &gs_vertex_count) srcs[URB_LOGICAL_SRC_PER_SLOT_OFFSETS] = per_slot_offsets; srcs[URB_LOGICAL_SRC_DATA] = retype(brw_allocate_vgrf_units(*this, (dispatch_width / 8) * length), BRW_TYPE_F); - srcs[URB_LOGICAL_SRC_COMPONENTS] = brw_imm_ud(length); abld.LOAD_PAYLOAD(srcs[URB_LOGICAL_SRC_DATA], sources, length, 0); - brw_inst *inst = abld.URB_WRITE(srcs, ARRAY_SIZE(srcs)); + brw_urb_inst *urb = abld.URB_WRITE(srcs, ARRAY_SIZE(srcs)); + urb->components = length; /* For Wa_1805992985 one needs additional write in the end. */ if (intel_needs_workaround(devinfo, 1805992985) && stage == MESA_SHADER_TESS_EVAL) - inst->eot = false; + urb->eot = false; else - inst->eot = slot == last_slot && stage != MESA_SHADER_GEOMETRY; + urb->eot = slot == last_slot && stage != MESA_SHADER_GEOMETRY; - inst->offset = urb_offset; + urb->offset = urb_offset; urb_offset = starting_urb_offset + slot + 1; length = 0; flush = false; @@ -287,11 +287,11 @@ brw_shader::emit_urb_writes(const brw_reg &gs_vertex_count) brw_reg srcs[URB_LOGICAL_NUM_SRCS]; srcs[URB_LOGICAL_SRC_HANDLE] = uniform_urb_handle; srcs[URB_LOGICAL_SRC_DATA] = payload; - srcs[URB_LOGICAL_SRC_COMPONENTS] = brw_imm_ud(1); - brw_inst *inst = bld.URB_WRITE(srcs, ARRAY_SIZE(srcs)); - inst->eot = true; - inst->offset = 1; + brw_urb_inst *urb = bld.URB_WRITE(srcs, ARRAY_SIZE(srcs)); + urb->eot = true; + urb->offset = 1; + urb->components = 1; return; } @@ -338,11 +338,11 @@ brw_shader::emit_urb_writes(const brw_reg &gs_vertex_count) srcs[URB_LOGICAL_SRC_HANDLE] = uniform_urb_handle; srcs[URB_LOGICAL_SRC_CHANNEL_MASK] = uniform_mask; srcs[URB_LOGICAL_SRC_DATA] = payload; - srcs[URB_LOGICAL_SRC_COMPONENTS] = brw_imm_ud(4); - brw_inst *inst = bld.exec_all().URB_WRITE(srcs, ARRAY_SIZE(srcs)); - inst->eot = true; - inst->offset = 0; + brw_urb_inst *urb = bld.exec_all().URB_WRITE(srcs, ARRAY_SIZE(srcs)); + urb->eot = true; + urb->offset = 0; + urb->components = 4; } }