From cefec430a3cde8192fc04af575ec30ee299e2b75 Mon Sep 17 00:00:00 2001 From: Alyssa Rosenzweig Date: Tue, 26 Jul 2022 10:09:06 -0400 Subject: [PATCH] pan/bi: Clear reg in squeeze_index MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit SSA is broken at this point. Let's not pretend otherwise. The numbering produced by squeeze_index already disambiguates what-used-to-be SSA variables and registers. A few shader-db changes because this shuffles the register allocation around because LCRA is stupid. total instructions in shared programs: 2658849 -> 2650196 (-0.33%) instructions in affected programs: 463733 -> 455080 (-1.87%) helped: 1089 HURT: 135 helped stats (abs) min: 1.0 max: 43.0 x̄: 8.20 x̃: 5 helped stats (rel) min: 0.11% max: 17.05% x̄: 2.28% x̃: 1.52% HURT stats (abs) min: 1.0 max: 7.0 x̄: 2.07 x̃: 2 HURT stats (rel) min: 0.10% max: 2.97% x̄: 1.03% x̃: 0.83% 95% mean confidence interval for instructions value: -7.52 -6.62 95% mean confidence interval for instructions %-change: -2.04% -1.78% Instructions are helped. total cycles in shared programs: 140617.52 -> 140613.14 (<.01%) cycles in affected programs: 227.45 -> 223.08 (-1.92%) helped: 45 HURT: 1 helped stats (abs) min: 0.015625 max: 0.4375 x̄: 0.10 x̃: 0 helped stats (rel) min: 0.43% max: 17.72% x̄: 2.79% x̃: 1.29% HURT stats (abs) min: 0.015625 max: 0.015625 x̄: 0.02 x̃: 0 HURT stats (rel) min: 1.47% max: 1.47% x̄: 1.47% x̃: 1.47% 95% mean confidence interval for cycles value: -0.12 -0.07 95% mean confidence interval for cycles %-change: -3.76% -1.64% Cycles are helped. total cvt in shared programs: 13877.61 -> 13742.41 (-0.97%) cvt in affected programs: 3432 -> 3296.80 (-3.94%) helped: 1089 HURT: 135 helped stats (abs) min: 0.015625 max: 0.671875 x̄: 0.13 x̃: 0 helped stats (rel) min: 0.18% max: 28.36% x̄: 5.05% x̃: 3.38% HURT stats (abs) min: 0.015625 max: 0.109375 x̄: 0.03 x̃: 0 HURT stats (rel) min: 0.15% max: 8.33% x̄: 2.87% x̃: 2.27% 95% mean confidence interval for cvt value: -0.12 -0.10 95% mean confidence interval for cvt %-change: -4.46% -3.88% Cvt are helped. total quadwords in shared programs: 1442328 -> 1437776 (-0.32%) quadwords in affected programs: 106240 -> 101688 (-4.28%) helped: 478 HURT: 17 helped stats (abs) min: 8.0 max: 24.0 x̄: 9.81 x̃: 8 helped stats (rel) min: 1.54% max: 20.00% x̄: 5.27% x̃: 3.70% HURT stats (abs) min: 8.0 max: 8.0 x̄: 8.00 x̃: 8 HURT stats (rel) min: 1.61% max: 14.29% x̄: 6.42% x̃: 6.25% 95% mean confidence interval for quadwords value: -9.61 -8.78 95% mean confidence interval for quadwords %-change: -5.20% -4.54% Quadwords are helped. total threads in shared programs: 53557 -> 53550 (-0.01%) threads in affected programs: 14 -> 7 (-50.00%) helped: 0 HURT: 7 HURT stats (abs) min: 1.0 max: 1.0 x̄: 1.00 x̃: 1 HURT stats (rel) min: 50.00% max: 50.00% x̄: 50.00% x̃: 50.00% 95% mean confidence interval for threads value: -1.00 -1.00 95% mean confidence interval for threads %-change: -50.00% -50.00% Threads are HURT. Signed-off-by: Alyssa Rosenzweig Part-of: --- src/panfrost/bifrost/bi_ra.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/src/panfrost/bifrost/bi_ra.c b/src/panfrost/bifrost/bi_ra.c index 4faccb9f295..dd27ac688ef 100644 --- a/src/panfrost/bifrost/bi_ra.c +++ b/src/panfrost/bifrost/bi_ra.c @@ -848,17 +848,19 @@ find_or_allocate_temp(unsigned *map, unsigned value, unsigned *alloc) static void squeeze_index(bi_context *ctx) { - unsigned *map = rzalloc_array(ctx, unsigned, ctx->ssa_alloc); + unsigned *map = rzalloc_array(ctx, unsigned, bi_max_temp(ctx)); ctx->ssa_alloc = 0; bi_foreach_instr_global(ctx, I) { bi_foreach_dest(I, d) { - I->dest[d].value = find_or_allocate_temp(map, I->dest[d].value, &ctx->ssa_alloc); + I->dest[d].value = find_or_allocate_temp(map, bi_get_node(I->dest[d]), &ctx->ssa_alloc); + I->dest[d].reg = false; } bi_foreach_src(I, s) { if (I->src[s].type == BI_INDEX_NORMAL) - I->src[s].value = find_or_allocate_temp(map, I->src[s].value, &ctx->ssa_alloc); + I->src[s].value = find_or_allocate_temp(map, bi_get_node(I->src[s]), &ctx->ssa_alloc); + I->src[s].reg = false; } }