From ce336097f1c3f77db89f663e6eb8fe7f20f2cacc Mon Sep 17 00:00:00 2001 From: Rob Clark Date: Sun, 5 Mar 2023 12:38:24 -0800 Subject: [PATCH] freedreno/a6xx: Fix designator initializer order Clang seems more relaxed about this, allowing C99 style initializers without requiring ordering. But unfortunately g++ is more picky :-/ TODO this doesn't completely fix everything with g++, namely sparse array initialization.. for ir3 driver-params, I think we can convert these to structs. But there are still one or two others to deal with. Signed-off-by: Rob Clark Part-of: --- src/freedreno/fdl/freedreno_layout.h | 6 ++- .../drivers/freedreno/a6xx/fd6_blend.c | 43 ++++++++++++------- .../drivers/freedreno/a6xx/fd6_blitter.c | 8 ++-- .../drivers/freedreno/a6xx/fd6_compute.c | 2 +- src/gallium/drivers/freedreno/a6xx/fd6_draw.c | 4 +- src/gallium/drivers/freedreno/a6xx/fd6_emit.c | 6 +-- src/gallium/drivers/freedreno/a6xx/fd6_emit.h | 26 ++++++----- src/gallium/drivers/freedreno/a6xx/fd6_gmem.c | 24 +++++++---- .../drivers/freedreno/a6xx/fd6_image.c | 2 +- .../drivers/freedreno/a6xx/fd6_program.c | 4 +- .../drivers/freedreno/a6xx/fd6_rasterizer.c | 36 ++++++++++------ .../drivers/freedreno/a6xx/fd6_screen.c | 5 ++- .../drivers/freedreno/a6xx/fd6_texture.c | 2 +- 13 files changed, 104 insertions(+), 64 deletions(-) diff --git a/src/freedreno/fdl/freedreno_layout.h b/src/freedreno/fdl/freedreno_layout.h index 5439d4fbbd9..e4c02aff47f 100644 --- a/src/freedreno/fdl/freedreno_layout.h +++ b/src/freedreno/fdl/freedreno_layout.h @@ -275,8 +275,10 @@ enum fdl_chroma_location { struct fdl_view_args { uint64_t iova; - uint32_t base_array_layer, base_miplevel; - uint32_t layer_count, level_count; + uint32_t base_miplevel; + uint32_t level_count; + uint32_t base_array_layer; + uint32_t layer_count; float min_lod_clamp; unsigned char swiz[4]; enum pipe_format format; diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_blend.c b/src/gallium/drivers/freedreno/a6xx/fd6_blend.c index 30933ca3998..863b70ec638 100644 --- a/src/gallium/drivers/freedreno/a6xx/fd6_blend.c +++ b/src/gallium/drivers/freedreno/a6xx/fd6_blend.c @@ -98,11 +98,16 @@ __fd6_setup_blend_variant(struct fd6_blend_stateobj *blend, .alpha_blend_opcode = blend_func(rt->alpha_func), .alpha_dest_factor = fd_blend_factor(rt->alpha_dst_factor), )); - OUT_REG(ring, A6XX_RB_MRT_CONTROL(i, .rop_code = rop, - .rop_enable = cso->logicop_enable, - .component_enable = rt->colormask, - .blend = rt->blend_enable, - .blend2 = rt->blend_enable, )); + OUT_REG(ring, + A6XX_RB_MRT_CONTROL( + i, + .blend = rt->blend_enable, + .blend2 = rt->blend_enable, + .rop_enable = cso->logicop_enable, + .rop_code = rop, + .component_enable = rt->colormask, + ) + ); if (rt->blend_enable) { mrt_blend |= (1 << i); @@ -126,19 +131,25 @@ __fd6_setup_blend_variant(struct fd6_blend_stateobj *blend, .dither_mode_mrt7 = cso->dither ? DITHER_ALWAYS : DITHER_DISABLE, )); - OUT_REG(ring, A6XX_SP_BLEND_CNTL(.enable_blend = mrt_blend, - .unk8 = true, - .alpha_to_coverage = cso->alpha_to_coverage, - .dual_color_in_enable = - blend->use_dual_src_blend, )); + OUT_REG(ring, + A6XX_SP_BLEND_CNTL( + .enable_blend = mrt_blend, + .unk8 = true, + .dual_color_in_enable = blend->use_dual_src_blend, + .alpha_to_coverage = cso->alpha_to_coverage, + ), + ); OUT_REG(ring, - A6XX_RB_BLEND_CNTL(.enable_blend = mrt_blend, - .alpha_to_coverage = cso->alpha_to_coverage, - .alpha_to_one = cso->alpha_to_one, - .independent_blend = cso->independent_blend_enable, - .sample_mask = sample_mask, - .dual_color_in_enable = blend->use_dual_src_blend, )); + A6XX_RB_BLEND_CNTL( + .enable_blend = mrt_blend, + .independent_blend = cso->independent_blend_enable, + .dual_color_in_enable = blend->use_dual_src_blend, + .alpha_to_coverage = cso->alpha_to_coverage, + .alpha_to_one = cso->alpha_to_one, + .sample_mask = sample_mask, + ), + ); so->sample_mask = sample_mask; diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_blitter.c b/src/gallium/drivers/freedreno/a6xx/fd6_blitter.c index 7632b415bed..58b8bed7910 100644 --- a/src/gallium/drivers/freedreno/a6xx/fd6_blitter.c +++ b/src/gallium/drivers/freedreno/a6xx/fd6_blitter.c @@ -565,8 +565,8 @@ emit_blit_dst(struct fd_ringbuffer *ring, struct pipe_resource *prsc, .color_format = fmt, .tile_mode = tile, .color_swap = swap, - .srgb = util_format_is_srgb(pfmt), .flags = ubwc_enabled, + .srgb = util_format_is_srgb(pfmt), ), A6XX_RB_2D_DST( .bo = dst->bo, @@ -610,13 +610,13 @@ emit_blit_src(struct fd_ringbuffer *ring, const struct pipe_blit_info *info, .color_format = sfmt, .tile_mode = stile, .color_swap = sswap, - .samples = samples, - .samples_average = (samples > MSAA_ONE) && !sample_0, .flags = subwc_enabled, .srgb = util_format_is_srgb(info->src.format), + .samples = samples, + .filter = (info->filter == PIPE_TEX_FILTER_LINEAR), + .samples_average = (samples > MSAA_ONE) && !sample_0, .unk20 = true, .unk22 = true, - .filter = (info->filter == PIPE_TEX_FILTER_LINEAR), ), A6XX_SP_PS_2D_SRC_SIZE( .width = width, diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_compute.c b/src/gallium/drivers/freedreno/a6xx/fd6_compute.c index 229f88e26d6..8dcfe929382 100644 --- a/src/gallium/drivers/freedreno/a6xx/fd6_compute.c +++ b/src/gallium/drivers/freedreno/a6xx/fd6_compute.c @@ -52,7 +52,7 @@ cs_program_emit(struct fd_context *ctx, struct fd_ringbuffer *ring, OUT_REG(ring, A6XX_HLSQ_INVALIDATE_CMD(.vs_state = true, .hs_state = true, .ds_state = true, .gs_state = true, .fs_state = true, .cs_state = true, - .gfx_ibo = true, .cs_ibo = true, )); + .cs_ibo = true, .gfx_ibo = true, )); OUT_PKT4(ring, REG_A6XX_HLSQ_CS_CNTL, 1); OUT_RING(ring, A6XX_HLSQ_CS_CNTL_CONSTLEN(v->constlen) | diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_draw.c b/src/gallium/drivers/freedreno/a6xx/fd6_draw.c index 027ad22c95e..4ee23d29dcf 100644 --- a/src/gallium/drivers/freedreno/a6xx/fd6_draw.c +++ b/src/gallium/drivers/freedreno/a6xx/fd6_draw.c @@ -439,9 +439,9 @@ fd6_clear_lrz(struct fd_batch *batch, struct fd_resource *zsbuf, double depth) a A6XX_HLSQ_INVALIDATE_CMD(.vs_state = true, .hs_state = true, .ds_state = true, .gs_state = true, .fs_state = true, .cs_state = true, - .gfx_ibo = true, .cs_ibo = true, + .cs_ibo = true, .gfx_ibo = true, .gfx_shared_const = true, - .gfx_bindless = 0x1f, .cs_bindless = 0x1f)); + .cs_bindless = 0x1f, .gfx_bindless = 0x1f)); emit_marker6(ring, 7); OUT_PKT7(ring, CP_SET_MARKER, 1); diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_emit.c b/src/gallium/drivers/freedreno/a6xx/fd6_emit.c index e50567c4a76..726dbe07872 100644 --- a/src/gallium/drivers/freedreno/a6xx/fd6_emit.c +++ b/src/gallium/drivers/freedreno/a6xx/fd6_emit.c @@ -751,10 +751,10 @@ fd6_emit_restore(struct fd_batch *batch, struct fd_ringbuffer *ring) A6XX_HLSQ_INVALIDATE_CMD(.vs_state = true, .hs_state = true, .ds_state = true, .gs_state = true, .fs_state = true, .cs_state = true, - .gfx_ibo = true, .cs_ibo = true, - .gfx_shared_const = true, + .cs_ibo = true, .gfx_ibo = true, .cs_shared_const = true, - .gfx_bindless = 0x1f, .cs_bindless = 0x1f)); + .gfx_shared_const = true, + .cs_bindless = 0x1f, .gfx_bindless = 0x1f)); OUT_WFI5(ring); diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_emit.h b/src/gallium/drivers/freedreno/a6xx/fd6_emit.h index 1545aa21ebe..b948482e3cc 100644 --- a/src/gallium/drivers/freedreno/a6xx/fd6_emit.h +++ b/src/gallium/drivers/freedreno/a6xx/fd6_emit.h @@ -137,24 +137,30 @@ fd6_state_emit(struct fd6_state *state, struct fd_ringbuffer *ring) } } +static inline unsigned +enable_mask(enum fd6_state_id group_id) +{ + switch (group_id) { + case FD6_GROUP_PROG: return ENABLE_DRAW; + case FD6_GROUP_PROG_BINNING: return CP_SET_DRAW_STATE__0_BINNING; + case FD6_GROUP_PROG_INTERP: return ENABLE_DRAW; + case FD6_GROUP_FS_TEX: return ENABLE_DRAW; + case FD6_GROUP_FS_BINDLESS: return ENABLE_DRAW; + case FD6_GROUP_PRIM_MODE_SYSMEM: return CP_SET_DRAW_STATE__0_SYSMEM | CP_SET_DRAW_STATE__0_BINNING; + case FD6_GROUP_PRIM_MODE_GMEM: return CP_SET_DRAW_STATE__0_GMEM; + default: return ENABLE_ALL; + } +} + static inline void fd6_state_take_group(struct fd6_state *state, struct fd_ringbuffer *stateobj, enum fd6_state_id group_id) { - static const unsigned enable_mask[32] = { - [FD6_GROUP_PROG] = ENABLE_DRAW, - [FD6_GROUP_PROG_BINNING] = CP_SET_DRAW_STATE__0_BINNING, - [FD6_GROUP_PROG_INTERP] = ENABLE_DRAW, - [FD6_GROUP_FS_TEX] = ENABLE_DRAW, - [FD6_GROUP_FS_BINDLESS] = ENABLE_DRAW, - [FD6_GROUP_PRIM_MODE_SYSMEM] = CP_SET_DRAW_STATE__0_SYSMEM | CP_SET_DRAW_STATE__0_BINNING, - [FD6_GROUP_PRIM_MODE_GMEM] = CP_SET_DRAW_STATE__0_GMEM, - }; assert(state->num_groups < ARRAY_SIZE(state->groups)); struct fd6_state_group *g = &state->groups[state->num_groups++]; g->stateobj = stateobj; g->group_id = group_id; - g->enable_mask = enable_mask[group_id] ? enable_mask[group_id] : ENABLE_ALL; + g->enable_mask = enable_mask(group_id); } static inline void diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c b/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c index d77fdfb9559..a8c5c063361 100644 --- a/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c +++ b/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c @@ -332,8 +332,8 @@ patch_fb_read_sysmem(struct fd_batch *batch) .base_array_layer = psurf->u.tex.first_layer, .layer_count = 1, - .format = psurf->format, .swiz = {PIPE_SWIZZLE_X, PIPE_SWIZZLE_Y, PIPE_SWIZZLE_Z, PIPE_SWIZZLE_W}, + .format = psurf->format, .type = FDL_VIEW_TYPE_2D, .chroma_offsets = {FDL_CHROMA_LOCATION_COSITED_EVEN, @@ -1026,9 +1026,13 @@ emit_blit(struct fd_batch *batch, struct fd_ringbuffer *ring, uint32_t base, enum a3xx_msaa_samples samples = fd_msaa_samples(rsc->b.b.nr_samples); OUT_REG(ring, - A6XX_RB_BLIT_DST_INFO(.tile_mode = tile_mode, .samples = samples, - .color_format = format, .color_swap = swap, - .flags = ubwc_enabled), + A6XX_RB_BLIT_DST_INFO( + .tile_mode = tile_mode, + .flags = ubwc_enabled, + .samples = samples, + .color_swap = swap, + .color_format = format, + ), A6XX_RB_BLIT_DST(.bo = rsc->bo, .bo_offset = offset), A6XX_RB_BLIT_DST_PITCH(.a6xx_rb_blit_dst_pitch = stride), A6XX_RB_BLIT_DST_ARRAY_PITCH(.a6xx_rb_blit_dst_array_pitch = array_stride)); @@ -1050,10 +1054,14 @@ emit_restore_blit(struct fd_batch *batch, struct fd_ringbuffer *ring, { bool stencil = (buffer == FD_BUFFER_STENCIL); - OUT_REG(ring, A6XX_RB_BLIT_INFO(.gmem = true, .unk0 = true, - .depth = (buffer == FD_BUFFER_DEPTH), - .sample_0 = util_format_is_pure_integer( - psurf->format))); + OUT_REG(ring, + A6XX_RB_BLIT_INFO( + .unk0 = true, + .gmem = true, + .sample_0 = util_format_is_pure_integer(psurf->format), + .depth = (buffer == FD_BUFFER_DEPTH), + ), + ); emit_blit(batch, ring, base, psurf, stencil); } diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_image.c b/src/gallium/drivers/freedreno/a6xx/fd6_image.c index afd81560f11..85a9c6e80a8 100644 --- a/src/gallium/drivers/freedreno/a6xx/fd6_image.c +++ b/src/gallium/drivers/freedreno/a6xx/fd6_image.c @@ -81,9 +81,9 @@ fd6_image_descriptor(struct fd_context *ctx, const struct pipe_image_view *buf, .base_array_layer = buf->u.tex.first_layer, .layer_count = buf->u.tex.last_layer - buf->u.tex.first_layer + 1, - .format = buf->format, .swiz = {PIPE_SWIZZLE_X, PIPE_SWIZZLE_Y, PIPE_SWIZZLE_Z, PIPE_SWIZZLE_W}, + .format = buf->format, .type = fdl_type_from_pipe_target(buf->resource->target), .chroma_offsets = {FDL_CHROMA_LOCATION_COSITED_EVEN, diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_program.c b/src/gallium/drivers/freedreno/a6xx/fd6_program.c index deefe17be9d..99c7c94ea27 100644 --- a/src/gallium/drivers/freedreno/a6xx/fd6_program.c +++ b/src/gallium/drivers/freedreno/a6xx/fd6_program.c @@ -313,7 +313,7 @@ setup_config_stateobj(struct fd_context *ctx, struct fd6_program_state *state) OUT_REG(ring, A6XX_HLSQ_INVALIDATE_CMD(.vs_state = true, .hs_state = true, .ds_state = true, .gs_state = true, .fs_state = true, .cs_state = true, - .gfx_ibo = true, .cs_ibo = true, )); + .cs_ibo = true, .gfx_ibo = true, )); assert(state->vs->constlen >= state->bs->constlen); @@ -422,8 +422,8 @@ setup_stateobj(struct fd_ringbuffer *ring, struct fd_context *ctx, static const struct ir3_shader_variant dummy_fs = { .info = { - .max_half_reg = -1, .max_reg = -1, + .max_half_reg = -1, .max_const = -1, }, }; diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_rasterizer.c b/src/gallium/drivers/freedreno/a6xx/fd6_rasterizer.c index bc7276168a9..466cf8df208 100644 --- a/src/gallium/drivers/freedreno/a6xx/fd6_rasterizer.c +++ b/src/gallium/drivers/freedreno/a6xx/fd6_rasterizer.c @@ -52,19 +52,26 @@ __fd6_setup_rasterizer_stateobj(struct fd_context *ctx, psize_max = cso->point_size; } - OUT_REG(ring, A6XX_GRAS_CL_CNTL(.znear_clip_disable = !cso->depth_clip_near, - .zfar_clip_disable = !cso->depth_clip_far, - .z_clamp_enable = cso->depth_clamp, - .vp_clip_code_ignore = 1, - .zero_gb_scale_z = cso->clip_halfz)); + OUT_REG(ring, + A6XX_GRAS_CL_CNTL( + .znear_clip_disable = !cso->depth_clip_near, + .zfar_clip_disable = !cso->depth_clip_far, + .z_clamp_enable = cso->depth_clamp, + .zero_gb_scale_z = cso->clip_halfz, + .vp_clip_code_ignore = 1, + ), + ); OUT_REG(ring, - A6XX_GRAS_SU_CNTL(.linehalfwidth = cso->line_width / 2.0f, - .poly_offset = cso->offset_tri, - .line_mode = cso->multisample ? RECTANGULAR : BRESENHAM, - .cull_front = cso->cull_face & PIPE_FACE_FRONT, - .cull_back = cso->cull_face & PIPE_FACE_BACK, - .front_cw = !cso->front_ccw, )); + A6XX_GRAS_SU_CNTL( + .cull_front = cso->cull_face & PIPE_FACE_FRONT, + .cull_back = cso->cull_face & PIPE_FACE_BACK, + .front_cw = !cso->front_ccw, + .linehalfwidth = cso->line_width / 2.0f, + .poly_offset = cso->offset_tri, + .line_mode = cso->multisample ? RECTANGULAR : BRESENHAM, + ), + ); OUT_REG(ring, A6XX_GRAS_SU_POINT_MINMAX(.min = psize_min, .max = psize_max, ), @@ -75,8 +82,11 @@ __fd6_setup_rasterizer_stateobj(struct fd_context *ctx, A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(cso->offset_clamp)); OUT_REG(ring, - A6XX_PC_PRIMITIVE_CNTL_0(.provoking_vtx_last = !cso->flatshade_first, - .primitive_restart = primitive_restart, )); + A6XX_PC_PRIMITIVE_CNTL_0( + .primitive_restart = primitive_restart, + .provoking_vtx_last = !cso->flatshade_first, + ), + ); enum a6xx_polygon_mode mode = POLYMODE6_TRIANGLES; switch (cso->fill_front) { diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_screen.c b/src/gallium/drivers/freedreno/a6xx/fd6_screen.c index bcfc7945dae..010a151e227 100644 --- a/src/gallium/drivers/freedreno/a6xx/fd6_screen.c +++ b/src/gallium/drivers/freedreno/a6xx/fd6_screen.c @@ -133,11 +133,14 @@ fd6_screen_is_format_supported(struct pipe_screen *pscreen, static const enum pc_di_primtype primtypes[] = { [PIPE_PRIM_POINTS] = DI_PT_POINTLIST, [PIPE_PRIM_LINES] = DI_PT_LINELIST, - [PIPE_PRIM_LINE_STRIP] = DI_PT_LINESTRIP, [PIPE_PRIM_LINE_LOOP] = DI_PT_LINELOOP, + [PIPE_PRIM_LINE_STRIP] = DI_PT_LINESTRIP, [PIPE_PRIM_TRIANGLES] = DI_PT_TRILIST, [PIPE_PRIM_TRIANGLE_STRIP] = DI_PT_TRISTRIP, [PIPE_PRIM_TRIANGLE_FAN] = DI_PT_TRIFAN, + [PIPE_PRIM_QUADS] = DI_PT_NONE, /* unsupported */ + [PIPE_PRIM_QUAD_STRIP] = DI_PT_NONE, /* unsupported */ + [PIPE_PRIM_POLYGON] = DI_PT_NONE, /* unsupported */ [PIPE_PRIM_LINES_ADJACENCY] = DI_PT_LINE_ADJ, [PIPE_PRIM_LINE_STRIP_ADJACENCY] = DI_PT_LINESTRIP_ADJ, [PIPE_PRIM_TRIANGLES_ADJACENCY] = DI_PT_TRI_ADJ, diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_texture.c b/src/gallium/drivers/freedreno/a6xx/fd6_texture.c index 589c3dae94b..71293f193f7 100644 --- a/src/gallium/drivers/freedreno/a6xx/fd6_texture.c +++ b/src/gallium/drivers/freedreno/a6xx/fd6_texture.c @@ -398,9 +398,9 @@ fd6_sampler_view_update(struct fd_context *ctx, .base_array_layer = cso->u.tex.first_layer, .layer_count = cso->u.tex.last_layer - cso->u.tex.first_layer + 1, - .format = format, .swiz = {cso->swizzle_r, cso->swizzle_g, cso->swizzle_b, cso->swizzle_a}, + .format = format, .type = fdl_type_from_pipe_target(cso->target), .chroma_offsets = {FDL_CHROMA_LOCATION_COSITED_EVEN,