diff --git a/src/amd/vulkan/radv_nir_to_llvm.c b/src/amd/vulkan/radv_nir_to_llvm.c index 7ce3250efcb..ac3938abc4b 100644 --- a/src/amd/vulkan/radv_nir_to_llvm.c +++ b/src/amd/vulkan/radv_nir_to_llvm.c @@ -1172,11 +1172,7 @@ handle_vs_input_decl(struct radv_shader_context *ctx, LLVMValueRef input; LLVMValueRef buffer_index; unsigned attrib_count = glsl_count_attribute_slots(variable->type, true); - uint8_t input_usage_mask = - ctx->args->shader_info->vs.input_usage_mask[variable->data.location]; - unsigned num_input_channels = util_last_bit(input_usage_mask); - variable->data.driver_location = variable->data.location * 4; enum glsl_base_type type = glsl_get_base_type(variable->type); for (unsigned i = 0; i < attrib_count; ++i) { @@ -1187,6 +1183,12 @@ handle_vs_input_decl(struct radv_shader_context *ctx, unsigned num_format = (attrib_format >> 4) & 0x07; bool is_float = num_format != V_008F0C_BUF_NUM_FORMAT_UINT && num_format != V_008F0C_BUF_NUM_FORMAT_SINT; + uint8_t input_usage_mask = + ctx->args->shader_info->vs.input_usage_mask[variable->data.location + i]; + unsigned num_input_channels = util_last_bit(input_usage_mask); + + if (num_input_channels == 0) + continue; if (ctx->args->options->key.vs.instance_rate_inputs & (1u << attrib_index)) { uint32_t divisor = ctx->args->options->key.vs.instance_rate_divisors[attrib_index]; diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c index bdf7277f0b9..a7e9cb0f06d 100644 --- a/src/amd/vulkan/radv_shader.c +++ b/src/amd/vulkan/radv_shader.c @@ -760,11 +760,6 @@ radv_lower_io(struct radv_device *device, nir_shader *nir) if (nir->info.stage == MESA_SHADER_COMPUTE) return; - /* TODO: Lower IO for all stages with LLVM. */ - if (nir->info.stage == MESA_SHADER_VERTEX && - radv_use_llvm_for_stage(device, nir->info.stage)) - return; - if (nir->info.stage == MESA_SHADER_FRAGMENT) { NIR_PASS_V(nir, lower_view_index); nir_assign_io_var_locations(nir, nir_var_shader_in, &nir->num_inputs,