diff --git a/src/intel/compiler/brw_eu_validate.c b/src/intel/compiler/brw_eu_validate.c
index ff235673b7d..f7ad8ce066e 100644
--- a/src/intel/compiler/brw_eu_validate.c
+++ b/src/intel/compiler/brw_eu_validate.c
@@ -1137,7 +1137,8 @@ special_restrictions_for_mixed_float_mode(const struct brw_isa_info *isa,
     *    "No SIMD16 in mixed mode when destination is f32. Instruction
     *     execution size must be no more than 8."
     */
-   ERROR_IF(exec_size > 8 && dst_type == BRW_REGISTER_TYPE_F,
+   ERROR_IF(exec_size > 8 && dst_type == BRW_REGISTER_TYPE_F &&
+            opcode != BRW_OPCODE_MOV,
             "Mixed float mode with 32-bit float destination is limited "
             "to SIMD8");
 
@@ -1212,7 +1213,8 @@ special_restrictions_for_mixed_float_mode(const struct brw_isa_info *isa,
        *     Align1 and Align16."
        */
       ERROR_IF(exec_size > 8 && dst_is_packed &&
-               dst_type == BRW_REGISTER_TYPE_HF,
+               dst_type == BRW_REGISTER_TYPE_HF &&
+               opcode != BRW_OPCODE_MOV,
                "Align1 mixed float mode is limited to SIMD8 when destination "
                "is packed half-float");
 
diff --git a/src/intel/compiler/brw_fs_lower_simd_width.cpp b/src/intel/compiler/brw_fs_lower_simd_width.cpp
index 4ea06b00e8b..87b7a1b11a6 100644
--- a/src/intel/compiler/brw_fs_lower_simd_width.cpp
+++ b/src/intel/compiler/brw_fs_lower_simd_width.cpp
@@ -113,34 +113,27 @@ get_fpu_lowered_simd_width(const fs_visitor *shader,
    if (inst->is_3src(compiler) && !devinfo->supports_simd16_3src)
       max_width = MIN2(max_width, inst->exec_size / reg_count);
 
-   /* From the SKL PRM, Special Restrictions for Handling Mixed Mode
-    * Float Operations:
-    *
-    *    "No SIMD16 in mixed mode when destination is f32. Instruction
-    *     execution size must be no more than 8."
-    *
-    * FIXME: the simulator doesn't seem to complain if we don't do this and
-    * empirical testing with existing CTS tests show that they pass just fine
-    * without implementing this, however, since our interpretation of the PRM
-    * is that conversion MOVs between HF and F are still mixed-float
-    * instructions (and therefore subject to this restriction) we decided to
-    * split them to be safe. Might be useful to do additional investigation to
-    * lift the restriction if we can ensure that it is safe though, since these
-    * conversions are common when half-float types are involved since many
-    * instructions do not support HF types and conversions from/to F are
-    * required.
-    */
-   if (is_mixed_float_with_fp32_dst(inst) && devinfo->ver < 20)
-      max_width = MIN2(max_width, 8);
+   if (inst->opcode != BRW_OPCODE_MOV) {
+      /* From the SKL PRM, Special Restrictions for Handling Mixed Mode
+       * Float Operations:
+       *
+       *    "No SIMD16 in mixed mode when destination is f32. Instruction
+       *     execution size must be no more than 8."
+       *
+       * Testing indicates that this restriction does not apply to MOVs.
+       */
+      if (is_mixed_float_with_fp32_dst(inst) && devinfo->ver < 20)
+         max_width = MIN2(max_width, 8);
 
-   /* From the SKL PRM, Special Restrictions for Handling Mixed Mode
-    * Float Operations:
-    *
-    *    "No SIMD16 in mixed mode when destination is packed f16 for both
-    *     Align1 and Align16."
-    */
-   if (is_mixed_float_with_packed_fp16_dst(inst) && devinfo->ver < 20)
-      max_width = MIN2(max_width, 8);
+      /* From the SKL PRM, Special Restrictions for Handling Mixed Mode
+       * Float Operations:
+       *
+       *    "No SIMD16 in mixed mode when destination is packed f16 for both
+       *     Align1 and Align16."
+       */
+      if (is_mixed_float_with_packed_fp16_dst(inst) && devinfo->ver < 20)
+         max_width = MIN2(max_width, 8);
+   }
 
    /* Only power-of-two execution sizes are representable in the instruction
     * control fields.