From cd15dec66e05cbdc9a07394f32d3848f71457146 Mon Sep 17 00:00:00 2001 From: Connor Abbott Date: Thu, 25 Apr 2024 15:13:06 -0400 Subject: [PATCH] ir3: Don't scalarize all SSBO instructions Use the newly-introduced filter to only scalarize the instructions we need to scalarize. Part-of: --- src/freedreno/ir3/ir3_nir.c | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/src/freedreno/ir3/ir3_nir.c b/src/freedreno/ir3/ir3_nir.c index efae5d3ebee..ad93a8c2c0a 100644 --- a/src/freedreno/ir3/ir3_nir.c +++ b/src/freedreno/ir3/ir3_nir.c @@ -84,6 +84,24 @@ ir3_load_driver_ubo_indirect(nir_builder *b, unsigned components, (range - 1) * 16); } +static bool +ir3_nir_should_scalarize_mem(const nir_instr *instr, const void *data) +{ + const struct ir3_compiler *compiler = data; + const nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr); + + /* Scalarize load_ssbo's that we could otherwise lower to isam, + * as the tex cache benefit outweighs the benefit of vectorizing + */ + if ((intrin->intrinsic == nir_intrinsic_load_ssbo) && + (nir_intrinsic_access(intrin) & ACCESS_CAN_REORDER) && + compiler->has_isam_ssbo) { + return true; + } + + return false; +} + static bool ir3_nir_should_vectorize_mem(unsigned align_mul, unsigned align_offset, unsigned bit_size, unsigned num_components, @@ -707,7 +725,8 @@ ir3_nir_lower_variant(struct ir3_shader_variant *so, nir_shader *s) bool progress = false; - NIR_PASS_V(s, nir_lower_io_to_scalar, nir_var_mem_ssbo, NULL, NULL); + NIR_PASS_V(s, nir_lower_io_to_scalar, nir_var_mem_ssbo, + ir3_nir_should_scalarize_mem, so->compiler); if (so->key.has_gs || so->key.tessellation) { switch (so->type) {