From cc570dbada06e810788a045f27c3e14a841b9845 Mon Sep 17 00:00:00 2001 From: Rohan Garg Date: Fri, 30 Jun 2023 12:55:04 +0200 Subject: [PATCH] isl: enable CCS for 3D surfaces on gen12.5 and above Signed-off-by: Rohan Garg Reviewed-by: Nanley Chery Part-of: --- src/intel/isl/isl.c | 42 ++++++++++++++++++++++++++++++++++++------ 1 file changed, 36 insertions(+), 6 deletions(-) diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c index acd3aeaa5d9..3b3f1ac8788 100644 --- a/src/intel/isl/isl.c +++ b/src/intel/isl/isl.c @@ -3033,6 +3033,12 @@ isl_surf_supports_ccs(const struct isl_device *dev, return false; if (ISL_GFX_VER(dev) >= 12) { + /* Wa_1406738321: 3D textures need a blit to a new surface in order to + * perform a resolve. For now, just disable CCS on TGL. + */ + if (dev->info->verx10 == 120 && surf->dim == ISL_SURF_DIM_3D) + return false; + if (isl_surf_usage_is_stencil(surf->usage)) { /* HiZ and MCS aren't allowed with stencil */ assert(hiz_or_mcs_surf == NULL || hiz_or_mcs_surf->size_B == 0); @@ -3040,6 +3046,21 @@ isl_surf_supports_ccs(const struct isl_device *dev, /* Multi-sampled stencil cannot have CCS */ if (surf->samples > 1) return false; + + /* No CCS support for 3D Depth/Stencil values + * + * According to HSD 22015614752, there are issues with multiple engines + * accessing the same CCS cacheline in parallel. For 2D depth/stencil, + * we can upgrade to Tile64 to avoid any issues, + * but we can't do the same for 3D depth/stencil. + * + * For that case, we can't use Tile64 because the depth/stencil + * hardware can't actually output 3D Tile64 data. + * + * Let's just disable CCS instead. + */ + if (surf->dim == ISL_SURF_DIM_3D) + return false; } else if (isl_surf_usage_is_depth(surf->usage)) { const struct isl_surf *hiz_surf = hiz_or_mcs_surf; @@ -3047,6 +3068,21 @@ isl_surf_supports_ccs(const struct isl_device *dev, if (hiz_surf == NULL || hiz_surf->size_B == 0) return false; + /* No CCS support for 3D Depth/Stencil values + * + * According to HSD 22015614752, there are issues with multiple engines + * accessing the same CCS cacheline in parallel. For 2D depth/stencil, + * we can upgrade to Tile64 to avoid any issues, + * but we can't do the same for 3D depth/stencil. + * + * For that case, we can't use Tile64 because the depth/stencil + * hardware can't actually output 3D Tile64 data. + * + * Let's just disable CCS instead. + */ + if (surf->dim == ISL_SURF_DIM_3D) + return false; + assert(hiz_surf->usage & ISL_SURF_USAGE_HIZ_BIT); assert(hiz_surf->tiling == ISL_TILING_HIZ); assert(isl_format_is_hiz(hiz_surf->format)); @@ -3070,12 +3106,6 @@ isl_surf_supports_ccs(const struct isl_device *dev, if (surf->row_pitch_B % 512 != 0) return false; - /* TODO: According to Wa_1406738321, 3D textures need a blit to a new - * surface in order to perform a resolve. For now, just disable CCS. - */ - if (surf->dim == ISL_SURF_DIM_3D) - return false; - /* BSpec 44930: (Gfx12, Gfx12.5) * * "Compression of 3D Ys surfaces with 64 or 128 bpp is not supported