From cbd5724a6dfe9f382e0c00fe868cd1721fe76432 Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Tue, 25 Jan 2022 08:56:30 +0100 Subject: [PATCH] aco: implement nir_intrinsic_load_vrs_rates_amd MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Samuel Pitoiset Reviewed-by: Timur Kristóf Reviewed-by: Bas Nieuwenhuizen Part-of: --- src/amd/compiler/aco_instruction_selection.cpp | 5 +++++ src/amd/compiler/aco_instruction_selection_setup.cpp | 3 ++- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp index b6de2c7d3b8..85b440819dc 100644 --- a/src/amd/compiler/aco_instruction_selection.cpp +++ b/src/amd/compiler/aco_instruction_selection.cpp @@ -9029,6 +9029,11 @@ visit_intrinsic(isel_context* ctx, nir_intrinsic_instr* instr) ctx->arg_temps[ctx->args->ac.tes_patch_id.arg_index] = get_ssa_temp(ctx, instr->src[3].ssa); break; } + case nir_intrinsic_load_force_vrs_rates_amd: { + bld.copy(Definition(get_ssa_temp(ctx, &instr->dest.ssa)), + get_arg(ctx, ctx->args->ac.force_vrs_rates)); + break; + } default: isel_err(&instr->instr, "Unimplemented intrinsic instr"); abort(); diff --git a/src/amd/compiler/aco_instruction_selection_setup.cpp b/src/amd/compiler/aco_instruction_selection_setup.cpp index 7cfd616b135..4ffbad7a698 100644 --- a/src/amd/compiler/aco_instruction_selection_setup.cpp +++ b/src/amd/compiler/aco_instruction_selection_setup.cpp @@ -626,7 +626,8 @@ init_context(isel_context* ctx, nir_shader* shader) case nir_intrinsic_load_viewport_x_scale: case nir_intrinsic_load_viewport_y_scale: case nir_intrinsic_load_viewport_x_offset: - case nir_intrinsic_load_viewport_y_offset: type = RegType::sgpr; break; + case nir_intrinsic_load_viewport_y_offset: + case nir_intrinsic_load_force_vrs_rates_amd: type = RegType::sgpr; break; case nir_intrinsic_load_sample_id: case nir_intrinsic_load_sample_mask_in: case nir_intrinsic_load_input: