From ca37d4c925359183cb0f1fa18641e7ddfa221886 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Sat, 25 Sep 2021 12:47:28 -0400 Subject: [PATCH] radeonsi: decrease vertex count threshold for shader culling to 128 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit to match radv Reviewed-by: Timur Kristóf Part-of: --- src/gallium/drivers/radeonsi/si_state_shaders.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c b/src/gallium/drivers/radeonsi/si_state_shaders.c index 8a78c928fc3..c88b11d56a2 100644 --- a/src/gallium/drivers/radeonsi/si_state_shaders.c +++ b/src/gallium/drivers/radeonsi/si_state_shaders.c @@ -2984,7 +2984,7 @@ static void *si_create_shader_selector(struct pipe_context *ctx, sscreen->info.chip_class == GFX10_3 || (sscreen->info.chip_class == GFX10 && sscreen->info.is_pro_graphics)) { - sel->ngg_cull_vert_threshold = sscreen->info.num_se >= 3 ? 511 : 255; + sel->ngg_cull_vert_threshold = 128; } } else if (sel->info.stage == MESA_SHADER_TESS_EVAL) { if (sel->rast_prim == PIPE_PRIM_TRIANGLES &&