diff --git a/src/amd/compiler/aco_instruction_selection_setup.cpp b/src/amd/compiler/aco_instruction_selection_setup.cpp
index 12a6e5514fd..3ff7f50bf0f 100644
--- a/src/amd/compiler/aco_instruction_selection_setup.cpp
+++ b/src/amd/compiler/aco_instruction_selection_setup.cpp
@@ -903,7 +903,8 @@ setup_isel_context(Program* program, unsigned shader_count, struct nir_shader* c
    for (unsigned i = 0; i < shader_count; i++)
       scratch_size = std::max(scratch_size, shaders[i]->scratch_size);
 
-   ctx.program->config->scratch_bytes_per_wave = align(scratch_size * ctx.program->wave_size, 1024);
+   ctx.program->config->scratch_bytes_per_wave =
+      align(scratch_size * ctx.program->wave_size, ctx.program->dev.scratch_alloc_granule);
 
    unsigned nir_num_blocks = 0;
    for (unsigned i = 0; i < shader_count; i++)
diff --git a/src/amd/compiler/aco_ir.cpp b/src/amd/compiler/aco_ir.cpp
index 9fbedb9d9df..1dc0d5d9e1c 100644
--- a/src/amd/compiler/aco_ir.cpp
+++ b/src/amd/compiler/aco_ir.cpp
@@ -137,6 +137,8 @@ init_program(Program* program, Stage stage, const struct aco_shader_info* info,
       program->dev.sgpr_limit = 104;
    }
 
+   program->dev.scratch_alloc_granule = gfx_level >= GFX11 ? 256 : 1024;
+
    program->dev.max_wave64_per_simd = 10;
    if (program->gfx_level >= GFX10_3)
       program->dev.max_wave64_per_simd = 16;
diff --git a/src/amd/compiler/aco_ir.h b/src/amd/compiler/aco_ir.h
index 7d9a34bbaae..cbdd300117c 100644
--- a/src/amd/compiler/aco_ir.h
+++ b/src/amd/compiler/aco_ir.h
@@ -2122,6 +2122,7 @@ struct DeviceInfo {
    uint16_t sgpr_limit;
    uint16_t sgpr_alloc_granule;
    uint16_t vgpr_alloc_granule;
+   unsigned scratch_alloc_granule;
    unsigned max_wave64_per_simd;
    unsigned simd_per_cu;
    bool has_fast_fma32 = false;
diff --git a/src/amd/compiler/aco_spill.cpp b/src/amd/compiler/aco_spill.cpp
index 38a5cf8d475..49a4370aa47 100644
--- a/src/amd/compiler/aco_spill.cpp
+++ b/src/amd/compiler/aco_spill.cpp
@@ -1856,8 +1856,8 @@ assign_spill_slots(spill_ctx& ctx, unsigned spills_to_vgpr)
    }
 
    /* update required scratch memory */
-   ctx.program->config->scratch_bytes_per_wave +=
-      align(ctx.vgpr_spill_slots * 4 * ctx.program->wave_size, 1024);
+   ctx.program->config->scratch_bytes_per_wave += align(
+      ctx.vgpr_spill_slots * 4 * ctx.program->wave_size, ctx.program->dev.scratch_alloc_granule);
 
    /* SSA elimination inserts copies for logical phis right before p_logical_end
     * So if a linear vgpr is used between that p_logical_end and the branch,