diff --git a/src/freedreno/ir3/ir3_delay.c b/src/freedreno/ir3/ir3_delay.c
index 1d382b45a80..7a310f236e4 100644
--- a/src/freedreno/ir3/ir3_delay.c
+++ b/src/freedreno/ir3/ir3_delay.c
@@ -165,28 +165,6 @@ delay_calc_srcn_prera(struct ir3_block *block,
 				continue;
 
 			d = delay_calc_srcn_prera(block, src->def->instr, consumer, srcn);
-
-			/* A (rptN) instruction executes in consecutive cycles so
-			 * it's outputs are written in successive cycles.  And
-			 * likewise for it's (r)'d (incremented) inputs, they are
-			 * read on successive cycles.
-			 *
-			 * So we need to adjust the delay for (rptN)'s assigners
-			 * and consumers accordingly.
-			 *
-			 * Note that the dst of a (rptN) instruction is implicitly
-			 * (r) (the assigner case), although that is not the case
-			 * for src registers.  There is exactly one case, bary.f,
-			 * which has a vecN (collect) src that is not (r)'d.
-			 */
-			if ((assigner->opc == OPC_META_SPLIT) && src->def->instr->repeat) {
-				/* (rptN) assigner case: */
-				d -= MIN2(d, src->def->instr->repeat - assigner->split.off);
-			} else if ((assigner->opc == OPC_META_COLLECT) && consumer->repeat &&
-					(consumer->regs[srcn]->flags & IR3_REG_R)) {
-				d -= MIN2(d, n);
-			}
-
 			delay = MAX2(delay, d);
 		}
 	} else {