From c8de5a7479515ad4d5e0caaf889919b2fb81f105 Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Tue, 14 Oct 2025 15:56:55 +0200 Subject: [PATCH] radv: pass int_sel to radv_cs_emit_write_event_eop() Signed-off-by: Samuel Pitoiset Part-of: --- src/amd/vulkan/radv_cmd_buffer.c | 12 +++++++----- src/amd/vulkan/radv_cs.c | 21 +++++++++------------ src/amd/vulkan/radv_cs.h | 4 ++-- src/amd/vulkan/radv_perfcounter.c | 3 ++- src/amd/vulkan/radv_query.c | 9 ++++++--- src/amd/vulkan/radv_queue.c | 2 +- 6 files changed, 27 insertions(+), 24 deletions(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 356bfc0cb7d..c4ed6f3bad3 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -1527,8 +1527,8 @@ radv_flush_gang_semaphore(struct radv_cmd_buffer *cmd_buffer, struct radv_cmd_st ASSERTED unsigned cdw_max = radeon_check_space(device->ws, cs->b, 12); radv_cs_emit_write_event_eop(cs, pdev->info.gfx_level, V_028A90_BOTTOM_OF_PIPE_TS, 0, EOP_DST_SEL_MEM, - EOP_DATA_SEL_VALUE_32BIT, cmd_buffer->gang.sem.va + va_off, value, - cmd_buffer->gfx9_eop_bug_va); + EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM, EOP_DATA_SEL_VALUE_32BIT, + cmd_buffer->gang.sem.va + va_off, value, cmd_buffer->gfx9_eop_bug_va); assert(cs->b->cdw <= cdw_max); return true; @@ -14527,8 +14527,9 @@ write_event(struct radv_cmd_buffer *cmd_buffer, struct radv_event *event, VkPipe event_type = V_028A90_BOTTOM_OF_PIPE_TS; } - radv_cs_emit_write_event_eop(cs, pdev->info.gfx_level, event_type, 0, EOP_DST_SEL_MEM, EOP_DATA_SEL_VALUE_32BIT, - va, value, cmd_buffer->gfx9_eop_bug_va); + radv_cs_emit_write_event_eop(cs, pdev->info.gfx_level, event_type, 0, EOP_DST_SEL_MEM, + EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM, EOP_DATA_SEL_VALUE_32BIT, va, value, + cmd_buffer->gfx9_eop_bug_va); } assert(cs->b->cdw <= cdw_max); @@ -15154,7 +15155,8 @@ radv_CmdWriteBufferMarker2AMD(VkCommandBuffer commandBuffer, VkPipelineStageFlag ac_emit_cp_copy_data(cs->b, COPY_DATA_IMM, COPY_DATA_DST_MEM, marker, va, AC_CP_COPY_DATA_WR_CONFIRM); } else { radv_cs_emit_write_event_eop(cs, pdev->info.gfx_level, V_028A90_BOTTOM_OF_PIPE_TS, 0, EOP_DST_SEL_MEM, - EOP_DATA_SEL_VALUE_32BIT, va, marker, cmd_buffer->gfx9_eop_bug_va); + EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM, EOP_DATA_SEL_VALUE_32BIT, va, marker, + cmd_buffer->gfx9_eop_bug_va); } assert(cs->b->cdw <= cdw_max); diff --git a/src/amd/vulkan/radv_cs.c b/src/amd/vulkan/radv_cs.c index 00c1515d9d1..bb006a768b0 100644 --- a/src/amd/vulkan/radv_cs.c +++ b/src/amd/vulkan/radv_cs.c @@ -18,8 +18,8 @@ void radv_cs_emit_write_event_eop(struct radv_cmd_stream *cs, enum amd_gfx_level gfx_level, unsigned event, - unsigned event_flags, unsigned dst_sel, unsigned data_sel, uint64_t va, uint32_t new_fence, - uint64_t gfx9_eop_bug_va) + unsigned event_flags, unsigned dst_sel, unsigned int_sel, unsigned data_sel, uint64_t va, + uint32_t new_fence, uint64_t gfx9_eop_bug_va) { if (cs->hw_ip == AMD_IP_SDMA) { radv_sdma_emit_fence(cs, va, new_fence); @@ -33,12 +33,7 @@ radv_cs_emit_write_event_eop(struct radv_cmd_stream *cs, enum amd_gfx_level gfx_ const bool is_mec = cs->hw_ip == AMD_IP_COMPUTE && gfx_level >= GFX7; unsigned op = EVENT_TYPE(event) | EVENT_INDEX(event == V_028A90_CS_DONE || event == V_028A90_PS_DONE ? 6 : 5) | event_flags; - unsigned sel = EOP_DST_SEL(dst_sel) | EOP_DATA_SEL(data_sel); - - /* Wait for write confirmation before writing data, but don't send - * an interrupt. */ - if (data_sel != EOP_DATA_SEL_DISCARD) - sel |= EOP_INT_SEL(EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM); + unsigned sel = EOP_DST_SEL(dst_sel) | EOP_INT_SEL(int_sel) | EOP_DATA_SEL(data_sel); radeon_begin(cs); @@ -257,7 +252,8 @@ gfx10_cs_emit_cache_flush(struct radv_cmd_stream *cs, enum amd_gfx_level gfx_lev S_490_GLM_WB(glm_wb) | S_490_GLM_INV(glm_inv) | S_490_GLV_INV(glv_inv) | S_490_GL1_INV(gl1_inv) | S_490_GL2_INV(gl2_inv) | S_490_GL2_WB(gl2_wb) | S_490_SEQ(gcr_seq), - EOP_DST_SEL_MEM, EOP_DATA_SEL_VALUE_32BIT, flush_va, *flush_cnt, gfx9_eop_bug_va); + EOP_DST_SEL_MEM, EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM, EOP_DATA_SEL_VALUE_32BIT, + flush_va, *flush_cnt, gfx9_eop_bug_va); radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, flush_va, *flush_cnt, 0xffffffff); } @@ -338,7 +334,7 @@ radv_cs_emit_cache_flush(struct radeon_winsys *ws, struct radv_cmd_stream *cs, e /* Necessary for DCC */ if (gfx_level >= GFX8) { radv_cs_emit_write_event_eop(cs, gfx_level, V_028A90_FLUSH_AND_INV_CB_DATA_TS, 0, EOP_DST_SEL_MEM, - EOP_DATA_SEL_DISCARD, 0, 0, gfx9_eop_bug_va); + EOP_INT_SEL_NONE, EOP_DATA_SEL_DISCARD, 0, 0, gfx9_eop_bug_va); } *sqtt_flush_bits |= RGP_FLUSH_FLUSH_CB | RGP_FLUSH_INVAL_CB; @@ -424,8 +420,9 @@ radv_cs_emit_cache_flush(struct radeon_winsys *ws, struct radv_cmd_stream *cs, e assert(flush_cnt); (*flush_cnt)++; - radv_cs_emit_write_event_eop(cs, gfx_level, cb_db_event, tc_flags, EOP_DST_SEL_MEM, EOP_DATA_SEL_VALUE_32BIT, - flush_va, *flush_cnt, gfx9_eop_bug_va); + radv_cs_emit_write_event_eop(cs, gfx_level, cb_db_event, tc_flags, EOP_DST_SEL_MEM, + EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM, EOP_DATA_SEL_VALUE_32BIT, flush_va, + *flush_cnt, gfx9_eop_bug_va); radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, flush_va, *flush_cnt, 0xffffffff); } diff --git a/src/amd/vulkan/radv_cs.h b/src/amd/vulkan/radv_cs.h index 0962a385d97..84e76ffb3f6 100644 --- a/src/amd/vulkan/radv_cs.h +++ b/src/amd/vulkan/radv_cs.h @@ -379,8 +379,8 @@ radv_cs_write_data(const struct radv_device *device, struct radv_cmd_stream *cs, } void radv_cs_emit_write_event_eop(struct radv_cmd_stream *cs, enum amd_gfx_level gfx_level, unsigned event, - unsigned event_flags, unsigned dst_sel, unsigned data_sel, uint64_t va, - uint32_t new_fence, uint64_t gfx9_eop_bug_va); + unsigned event_flags, unsigned dst_sel, unsigned int_sel, unsigned data_sel, + uint64_t va, uint32_t new_fence, uint64_t gfx9_eop_bug_va); void radv_cs_emit_cache_flush(struct radeon_winsys *ws, struct radv_cmd_stream *cs, enum amd_gfx_level gfx_level, uint32_t *flush_cnt, uint64_t flush_va, enum radv_cmd_flush_bits flush_bits, diff --git a/src/amd/vulkan/radv_perfcounter.c b/src/amd/vulkan/radv_perfcounter.c index 44b3de85653..47bb283f64d 100644 --- a/src/amd/vulkan/radv_perfcounter.c +++ b/src/amd/vulkan/radv_perfcounter.c @@ -744,7 +744,8 @@ radv_pc_end_query(struct radv_cmd_buffer *cmd_buffer, struct radv_pc_query_pool uint64_t perf_ctr_va = radv_buffer_get_va(device->perf_counter_bo) + PERF_CTR_BO_FENCE_OFFSET; radv_cs_emit_write_event_eop(cs, pdev->info.gfx_level, V_028A90_BOTTOM_OF_PIPE_TS, 0, EOP_DST_SEL_MEM, - EOP_DATA_SEL_VALUE_32BIT, perf_ctr_va, 1, cmd_buffer->gfx9_fence_va); + EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM, EOP_DATA_SEL_VALUE_32BIT, perf_ctr_va, 1, + cmd_buffer->gfx9_fence_va); radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, perf_ctr_va, 1, 0xffffffff); radv_pc_wait_idle(cmd_buffer); diff --git a/src/amd/vulkan/radv_query.c b/src/amd/vulkan/radv_query.c index a1a9c883ee3..ab106668c13 100644 --- a/src/amd/vulkan/radv_query.c +++ b/src/amd/vulkan/radv_query.c @@ -763,7 +763,8 @@ radv_end_pipeline_stat_query(struct radv_cmd_buffer *cmd_buffer, struct radv_que } radv_cs_emit_write_event_eop(cs, pdev->info.gfx_level, V_028A90_BOTTOM_OF_PIPE_TS, 0, EOP_DST_SEL_MEM, - EOP_DATA_SEL_VALUE_32BIT, avail_va, 1, cmd_buffer->gfx9_eop_bug_va); + EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM, EOP_DATA_SEL_VALUE_32BIT, avail_va, 1, + cmd_buffer->gfx9_eop_bug_va); } static void @@ -1634,7 +1635,8 @@ radv_end_ms_prim_query(struct radv_cmd_buffer *cmd_buffer, uint64_t va, uint64_t radv_emit_event_write(&pdev->info, cs, RADV_EVENT_WRITE_PIPELINE_STAT, va); radv_cs_emit_write_event_eop(cs, pdev->info.gfx_level, V_028A90_BOTTOM_OF_PIPE_TS, 0, EOP_DST_SEL_MEM, - EOP_DATA_SEL_VALUE_32BIT, avail_va, 1, cmd_buffer->gfx9_eop_bug_va); + EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM, EOP_DATA_SEL_VALUE_32BIT, avail_va, 1, + cmd_buffer->gfx9_eop_bug_va); } else { gfx10_copy_shader_query_gfx(cmd_buffer, true, RADV_SHADER_QUERY_MS_PRIM_GEN_OFFSET, va + 8); ac_emit_write_data_imm(cs->b, V_370_ME, va + 12, 0x80000000); @@ -2721,7 +2723,8 @@ radv_write_timestamp(struct radv_cmd_buffer *cmd_buffer, uint64_t va, VkPipeline AC_CP_COPY_DATA_WR_CONFIRM | AC_CP_COPY_DATA_COUNT_SEL); } else { radv_cs_emit_write_event_eop(cs, pdev->info.gfx_level, V_028A90_BOTTOM_OF_PIPE_TS, 0, EOP_DST_SEL_MEM, - EOP_DATA_SEL_TIMESTAMP, va, 0, cmd_buffer->gfx9_eop_bug_va); + EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM, EOP_DATA_SEL_TIMESTAMP, va, 0, + cmd_buffer->gfx9_eop_bug_va); } } diff --git a/src/amd/vulkan/radv_queue.c b/src/amd/vulkan/radv_queue.c index 290119f7980..09af3b12c01 100644 --- a/src/amd/vulkan/radv_queue.c +++ b/src/amd/vulkan/radv_queue.c @@ -1404,7 +1404,7 @@ radv_create_gang_wait_preambles_postambles(struct radv_queue *queue) radv_cp_wait_mem(leader_post_cs, WAIT_REG_MEM_GREATER_OR_EQUAL, leader_wait_va, 1, 0xffffffff); radv_cs_write_data(device, leader_post_cs, V_370_ME, leader_wait_va, 1, &zero, false); radv_cs_emit_write_event_eop(ace_post_cs, pdev->info.gfx_level, V_028A90_BOTTOM_OF_PIPE_TS, 0, EOP_DST_SEL_MEM, - EOP_DATA_SEL_VALUE_32BIT, leader_wait_va, 1, 0); + EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM, EOP_DATA_SEL_VALUE_32BIT, leader_wait_va, 1, 0); r = radv_finalize_cmd_stream(device, leader_pre_cs); if (r != VK_SUCCESS)