aco: implement load_shared2_amd/store_shared2_amd
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com> Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13778>
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@@ -725,6 +725,7 @@ init_context(isel_context* ctx, nir_shader* shader)
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case nir_intrinsic_load_cull_small_prim_precision_amd:
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case nir_intrinsic_load_vector_arg_amd: type = RegType::vgpr; break;
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case nir_intrinsic_load_shared:
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case nir_intrinsic_load_shared2_amd:
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/* When the result of these loads is only used by cross-lane instructions,
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* it is beneficial to use a VGPR destination. This is because this allows
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* to put the s_waitcnt further down, which decreases latency.
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