From c8830a1a79957d33d09b051ace49410f1bbed52f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Daniel=20Sch=C3=BCrmann?= Date: Fri, 10 Oct 2025 09:15:24 +0200 Subject: [PATCH] radv: delay ac_nir_lower_mem_access_bit_sizes Totals from 937 (1.17% of 79839) affected shaders: (Navi48) MaxWaves: 25196 -> 25272 (+0.30%); split: +0.33%, -0.03% Instrs: 619389 -> 617586 (-0.29%); split: -0.38%, +0.09% CodeSize: 3161156 -> 3147008 (-0.45%); split: -0.49%, +0.04% VGPRs: 54456 -> 54300 (-0.29%); split: -0.31%, +0.02% Latency: 1548791 -> 1550501 (+0.11%); split: -0.16%, +0.27% InvThroughput: 233599 -> 233561 (-0.02%); split: -0.10%, +0.08% Copies: 42820 -> 42799 (-0.05%); split: -0.63%, +0.58% PreVGPRs: 43480 -> 43479 (-0.00%) VALU: 348357 -> 348358 (+0.00%); split: -0.08%, +0.08% Part-of: --- src/amd/vulkan/radv_pipeline.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 548c8cb79fd..312e8e57328 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -547,8 +547,6 @@ radv_postprocess_nir(struct radv_device *device, const struct radv_graphics_stat NIR_PASS(_, stage->nir, nir_clear_shared_memory, shared_size, chunk_size); } - NIR_PASS(_, stage->nir, ac_nir_lower_mem_access_bit_sizes, gfx_level, use_llvm); - /* This must be after lowering resources to descriptor loads and before lowering intrinsics * to args and lowering int64. */ @@ -575,6 +573,7 @@ radv_postprocess_nir(struct radv_device *device, const struct radv_graphics_stat NIR_PASS(_, stage->nir, nir_opt_constant_folding); NIR_PASS(_, stage->nir, nir_opt_cse); NIR_PASS(_, stage->nir, nir_opt_shrink_vectors, true); + NIR_PASS(_, stage->nir, ac_nir_lower_mem_access_bit_sizes, gfx_level, use_llvm); nir_load_store_vectorize_options late_vectorize_opts = { .modes = @@ -588,9 +587,9 @@ radv_postprocess_nir(struct radv_device *device, const struct radv_graphics_stat .has_shared2_amd = gfx_level >= GFX7, }; NIR_PASS(_, stage->nir, nir_opt_load_store_vectorize, &late_vectorize_opts); - NIR_PASS(_, stage->nir, ac_nir_lower_mem_access_bit_sizes, gfx_level, use_llvm); } + NIR_PASS(_, stage->nir, ac_nir_lower_mem_access_bit_sizes, gfx_level, use_llvm); NIR_PASS(_, stage->nir, ac_nir_lower_global_access); NIR_PASS(_, stage->nir, nir_lower_int64);