From c82d70d3ec46ae922f6a159f22bc44171010026b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Daniel=20Sch=C3=BCrmann?= Date: Thu, 17 Jul 2025 11:33:14 +0200 Subject: [PATCH] radv: delay lowering int64 Part-of: --- src/amd/vulkan/radv_pipeline.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 652852940d1..8c792db6125 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -549,8 +549,6 @@ radv_postprocess_nir(struct radv_device *device, const struct radv_graphics_stat if (!radv_use_llvm_for_stage(pdev, stage->stage)) ac_nir_optimize_uniform_atomics(stage->nir); - NIR_PASS(_, stage->nir, nir_lower_int64); - NIR_PASS(_, stage->nir, nir_opt_idiv_const, 8); NIR_PASS(_, stage->nir, nir_lower_idiv, @@ -588,6 +586,7 @@ radv_postprocess_nir(struct radv_device *device, const struct radv_graphics_stat } NIR_PASS(_, stage->nir, ac_nir_lower_global_access); + NIR_PASS(_, stage->nir, nir_lower_int64); radv_optimize_nir_algebraic( stage->nir, io_to_mem || lowered_ngg || stage->stage == MESA_SHADER_COMPUTE || stage->stage == MESA_SHADER_TASK,