From c7a509f55c667fc7170679f12f30d5da04726291 Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Tue, 10 Sep 2024 16:14:34 +0200 Subject: [PATCH] radv: update PGM register for TES+GS compiled separately with ESO Not sure why 0xB210 works on GFX10+ because it's supposed to be 0xB320 with/without NGG... Signed-off-by: Samuel Pitoiset Part-of: --- src/amd/vulkan/radv_cmd_buffer.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index cec9ae9f558..6ece7064042 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -2318,7 +2318,13 @@ radv_emit_tess_eval_shader(struct radv_cmd_buffer *cmd_buffer) radv_shader_combine_cfg_tes_gs(tes, gs, &rsrc1, &rsrc2); - radeon_set_sh_reg(cmd_buffer->cs, R_00B210_SPI_SHADER_PGM_LO_ES, tes->va >> 8); + if (pdev->info.gfx_level >= GFX12) { + radeon_set_sh_reg(cmd_buffer->cs, R_00B224_SPI_SHADER_PGM_LO_ES, tes->va >> 8); + } else if (pdev->info.gfx_level >= GFX10) { + radeon_set_sh_reg(cmd_buffer->cs, R_00B320_SPI_SHADER_PGM_LO_ES, tes->va >> 8); + } else { + radeon_set_sh_reg(cmd_buffer->cs, R_00B210_SPI_SHADER_PGM_LO_ES, tes->va >> 8); + } unsigned lds_size; if (gs->info.is_ngg) {