From c750ab8a389b82795bb1509250711671c19f583d Mon Sep 17 00:00:00 2001 From: Icecream95 Date: Fri, 10 Dec 2021 23:40:01 +1300 Subject: [PATCH] pan/mdg: Fix mask usage when filling before a spill Check the bytemask against 0xFFFF rather than 0xF so that the fill is skipped for a .xyzw write rather than a .x write. Set the mask on the store to 0xF when doing a read so that all components are written back. Fixes: 31d26ebf1b9 ("pan/mdg: Fill from TLS before spilling non-SSA nodes") Part-of: --- src/panfrost/midgard/midgard_ra.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/src/panfrost/midgard/midgard_ra.c b/src/panfrost/midgard/midgard_ra.c index e3922639432..dea96086948 100644 --- a/src/panfrost/midgard/midgard_ra.c +++ b/src/panfrost/midgard/midgard_ra.c @@ -946,10 +946,15 @@ mir_spill_register( } else { unsigned dest = spill_index++; - if (write_count > 1 && mir_bytemask(ins) != 0xF) { + unsigned bytemask = mir_bytemask(ins); + unsigned write_mask = mir_from_bytemask(mir_round_bytemask_up( + bytemask, 32), 32); + + if (write_count > 1 && bytemask != 0xFFFF) { midgard_instruction read = v_load_store_scratch(dest, spill_slot, false, 0xF); mir_insert_instruction_before_scheduled(ctx, block, ins, read); + write_mask = 0xF; } ins->dest = dest; @@ -977,7 +982,7 @@ mir_spill_register( dest = spill_index++; midgard_instruction st = - v_load_store_scratch(dest, spill_slot, true, ins->mask); + v_load_store_scratch(dest, spill_slot, true, write_mask); mir_insert_instruction_after_scheduled(ctx, block, ins, st); if (move) {