From c6757cb8f08dea50a63059316446292fc2a5477f Mon Sep 17 00:00:00 2001
From: Rohan Garg <rohan.garg@intel.com>
Date: Mon, 10 Feb 2025 17:11:17 +0100
Subject: [PATCH] isl: enable CPB compression

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10760
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20741>
---
 src/intel/genxml/gen125.xml        | 2 +-
 src/intel/isl/isl.c                | 6 ------
 src/intel/isl/isl.h                | 5 +++++
 src/intel/isl/isl_emit_cpb.c       | 8 +++-----
 src/intel/vulkan/genX_cmd_buffer.c | 1 +
 5 files changed, 10 insertions(+), 12 deletions(-)

diff --git a/src/intel/genxml/gen125.xml b/src/intel/genxml/gen125.xml
index 6766aed98a3..09ef0f3a2dc 100644
--- a/src/intel/genxml/gen125.xml
+++ b/src/intel/genxml/gen125.xml
@@ -634,7 +634,7 @@
     <field name="Command SubType" start="27" end="28" type="uint" default="3" />
     <field name="Command Type" start="29" end="31" type="uint" default="3" />
     <field name="Surface Pitch" start="32" end="48" type="uint" />
-    <field name="CPCB Compression Enable" start="57" end="57" type="bool" />
+    <field name="Lossless Compression Enable" start="57" end="57" type="bool" />
     <field name="Surface Type" start="61" end="63" type="uint" />
     <field name="Surface Base Address" start="64" end="127" type="address" />
     <field name="Width" start="129" end="142" type="uint" />
diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index 60aa91ab0ed..06e1351cc3e 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -3620,12 +3620,6 @@ _isl_surf_info_supports_ccs(const struct isl_device *dev,
    if (usage & ISL_SURF_USAGE_DISABLE_AUX_BIT)
       return false;
 
-   /* TODO: Disable for now, as we're not sure about the meaning of
-    * 3DSTATE_CPSIZE_CONTROL_BUFFER::CPCBCompressionEnable
-    */
-   if (isl_surf_usage_is_cpb(usage) && dev->info->ver < 20)
-      return false;
-
    if (INTEL_DEBUG(DEBUG_NO_CCS))
       return false;
 
diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h
index 63c23e90d6f..2bb51c4f100 100644
--- a/src/intel/isl/isl.h
+++ b/src/intel/isl/isl.h
@@ -1978,6 +1978,11 @@ struct isl_cpb_emit_info {
     * The Memory Object Control state for the surface.
     */
    uint32_t mocs;
+
+   /**
+    * Aux usage of the CPB surface
+    */
+   enum isl_aux_usage aux_usage;
 };
 
 enum isl_surf_param {
diff --git a/src/intel/isl/isl_emit_cpb.c b/src/intel/isl/isl_emit_cpb.c
index e53055d13d0..2af2064d066 100644
--- a/src/intel/isl/isl_emit_cpb.c
+++ b/src/intel/isl/isl_emit_cpb.c
@@ -105,14 +105,12 @@ isl_genX(emit_cpb_control_s)(const struct isl_device *dev, void *batch,
       cpb.SurfaceBaseAddress     = info->address;
 
       cpb.MipTailStartLOD        = info->surf->miptail_start_level;
-      /* TODO:
-       *
-       * cpb.CPCBCompressionEnable is this CCS compression? Currently disabled
-       * in isl_surf_supports_ccs() for CPB buffers.
-       */
 #if GFX_VER >= 20
       cpb.CompressionFormat  =
          isl_get_render_compression_format(info->surf->format);
+#else
+      cpb.LosslessCompressionEnable =
+         isl_aux_usage_has_compression(info->aux_usage);
 #endif
    } else {
       cpb.SurfaceType  = SURFTYPE_NULL;
diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c
index 4f42eb1a9c3..3fcefa579c1 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -5181,6 +5181,7 @@ cmd_buffer_emit_cps_control_buffer(struct anv_cmd_buffer *cmd_buffer,
 
       info.view = &fsr_iview->planes[0].isl;
       info.surf = &fsr_iview->image->planes[0].primary_surface.isl;
+      info.aux_usage = fsr_iview->image->planes[0].aux_usage;
       info.address = anv_address_physical(addr);
       info.mocs =
          anv_mocs(device, fsr_iview->image->bindings[0].address.bo,