diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index a27ee8e2f37..e246bd605f7 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -875,6 +875,18 @@ radv_image_is_pipe_misaligned(const struct radv_device *device, const struct rad
 
    assert(gpu_info->gfx_level >= GFX10);
 
+   /* Add a special case for mips in the metadata mip-tail for GFX11. */
+   if (pdev->info.gfx_level >= GFX11) {
+      if (image->vk.mip_levels > 1 && (radv_image_has_dcc(image) || radv_image_has_htile(image))) {
+         for (unsigned i = 0; i < image->plane_count; ++i) {
+            const struct radeon_surf *surf = &image->planes[i].surface;
+
+            if (surf->num_meta_levels != image->vk.mip_levels)
+               return true;
+         }
+      }
+   }
+
    for (unsigned i = 0; i < image->plane_count; ++i) {
       VkFormat fmt = radv_image_get_plane_format(pdev, image, i);
       int log2_bpp = util_logbase2(vk_format_get_blocksize(fmt));
@@ -923,18 +935,6 @@ radv_image_is_l2_coherent(const struct radv_device *device, const struct radv_im
    if (pdev->info.gfx_level >= GFX12) {
       return true; /* Everything is coherent with TC L2. */
    } else if (pdev->info.gfx_level >= GFX10) {
-      /* Add a special case for mips in the metadata mip-tail for GFX11. */
-      if (pdev->info.gfx_level >= GFX11) {
-         if (image->vk.mip_levels > 1 && (radv_image_has_dcc(image) || radv_image_has_htile(image))) {
-            for (unsigned i = 0; i < image->plane_count; ++i) {
-               const struct radeon_surf *surf = &image->planes[i].surface;
-
-               if (surf->num_meta_levels != image->vk.mip_levels)
-                  return false;
-            }
-         }
-      }
-
       return !radv_image_is_pipe_misaligned(device, image);
    } else if (pdev->info.gfx_level == GFX9) {
       if (image->vk.samples == 1 &&