From c5806422a53c1aa220cc1dfacad5503aa045eaf9 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= <marek.olsak@amd.com>
Date: Fri, 19 May 2023 00:02:04 -0400
Subject: [PATCH] radeonsi: reduce the supported compute grid size

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23216>
---
 src/gallium/drivers/radeonsi/si_get.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_get.c b/src/gallium/drivers/radeonsi/si_get.c
index 173dfa56207..93a0c7cbc63 100644
--- a/src/gallium/drivers/radeonsi/si_get.c
+++ b/src/gallium/drivers/radeonsi/si_get.c
@@ -994,9 +994,10 @@ static int si_get_compute_param(struct pipe_screen *screen, enum pipe_shader_ir
    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
       if (ret) {
          uint64_t *grid_size = ret;
+         /* Use this size, so that internal counters don't overflow 64 bits. */
          grid_size[0] = UINT32_MAX;
-         grid_size[1] = UINT32_MAX;
-         grid_size[2] = UINT32_MAX;
+         grid_size[1] = UINT16_MAX;
+         grid_size[2] = UINT16_MAX;
       }
       return 3 * sizeof(uint64_t);