diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c
index 312e7c17f87..64198871472 100644
--- a/src/amd/vulkan/si_cmd_buffer.c
+++ b/src/amd/vulkan/si_cmd_buffer.c
@@ -1541,8 +1541,35 @@ si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va, unsigned siz
    uint64_t aligned_va = va & ~(SI_CPDMA_ALIGNMENT - 1);
    uint64_t aligned_size =
       ((va + size + SI_CPDMA_ALIGNMENT - 1) & ~(SI_CPDMA_ALIGNMENT - 1)) - aligned_va;
+   struct radeon_cmdbuf *cs = cmd_buffer->cs;
+   uint32_t header = 0, command = 0;
 
-   si_emit_cp_dma(cmd_buffer, aligned_va, aligned_va, aligned_size, CP_DMA_USE_L2);
+   assert(size <= cp_dma_max_byte_count(cmd_buffer));
+
+   radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 9);
+
+   if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
+      command |= S_415_BYTE_COUNT_GFX9(aligned_size) |
+                 S_415_DISABLE_WR_CONFIRM_GFX9(1);
+      header |= S_411_DST_SEL(V_411_NOWHERE);
+   } else {
+      command |= S_415_BYTE_COUNT_GFX6(aligned_size) |
+                 S_415_DISABLE_WR_CONFIRM_GFX6(1);
+      header |= S_411_DST_SEL(V_411_DST_ADDR_TC_L2);
+   }
+
+   header |= S_411_SRC_SEL(V_411_SRC_ADDR_TC_L2);
+
+   radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, cmd_buffer->state.predicating));
+   radeon_emit(cs, header);
+   radeon_emit(cs, aligned_va);       /* SRC_ADDR_LO [31:0] */
+   radeon_emit(cs, aligned_va >> 32); /* SRC_ADDR_HI [31:0] */
+   radeon_emit(cs, aligned_va);       /* DST_ADDR_LO [31:0] */
+   radeon_emit(cs, aligned_va >> 32); /* DST_ADDR_HI [31:0] */
+   radeon_emit(cs, command);
+
+   if (unlikely(cmd_buffer->device->trace_bo))
+      radv_cmd_buffer_trace_emit(cmd_buffer);
 }
 
 static void