From c42830c64a18ec9d69b591640cf8e65976f924e0 Mon Sep 17 00:00:00 2001 From: Ian Romanick Date: Tue, 9 Jan 2024 13:11:00 -0800 Subject: [PATCH] intel/fs: Use constant of same type to write flag Otherwise the compiler generates an extra MOV to load the constant into a register first because reasons. :shrug: vote_any, vote_all, vote_ieq, and vote_feq handling already do this. No shader-db changes on any Intel plaform. Fossil-db results: All Intel platforms had similar results. (Ice Lake shown) Totals: Instrs: 165592451 -> 165557937 (-0.02%) Cycles: 15133282615 -> 15133059360 (-0.00%); split: -0.00%, +0.00% Totals from 33779 (5.15% of 656115) affected shaders: Instrs: 4396576 -> 4362062 (-0.79%) Cycles: 86867412 -> 86644157 (-0.26%); split: -0.37%, +0.11% Reviewed-by: Lionel Landwerlin Part-of: --- src/intel/compiler/brw_fs_nir.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index ef29927dd7a..7f043c0fbe9 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++ b/src/intel/compiler/brw_fs_nir.cpp @@ -7289,7 +7289,7 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, if (s.dispatch_width == 32) flag.type = BRW_REGISTER_TYPE_UD; - bld.exec_all().group(1, 0).MOV(flag, brw_imm_ud(0u)); + bld.exec_all().group(1, 0).MOV(flag, retype(brw_imm_ud(0u), flag.type)); bld.CMP(bld.null_reg_ud(), value, brw_imm_ud(0u), BRW_CONDITIONAL_NZ); if (instr->def.bit_size > 32) {