From c3c05ffb5fab542a43520c139ce1e52955dfdb81 Mon Sep 17 00:00:00 2001 From: Michael Cheng Date: Sun, 15 Dec 2024 15:34:57 -0800 Subject: [PATCH] intel : Expose Shader hashes for utrace and Perfetto MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch exposes shader hashes (computes and draws) to Perfetto and utrace. By including these hashes in traces, developers can correlate compute and draw calls with their assoicated ASM dumps when analyzing the traces. To achieve this, intel_tracepoint.py has been reworked to preprocess tracepoint arguments dynamically. Any argument containing "hash" in its variable name is now forrmated as hexadecimal before being passed to the tracepoint definition. Signed-off-by: Michael Reviewed-by: José Roberto de Souza Part-of: --- src/gallium/drivers/iris/iris_state.c | 10 ++-- src/intel/ds/intel_tracepoints.py | 55 +++++++++++++++++----- src/intel/vulkan/genX_cmd_compute.c | 9 ++-- src/intel/vulkan/genX_cmd_draw.c | 60 +++++++++++++++++++----- src/intel/vulkan_hasvk/genX_cmd_buffer.c | 24 +++++----- 5 files changed, 112 insertions(+), 46 deletions(-) diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c index 317a492d853..b642e4f141f 100644 --- a/src/gallium/drivers/iris/iris_state.c +++ b/src/gallium/drivers/iris/iris_state.c @@ -8668,7 +8668,7 @@ iris_upload_render_state(struct iris_context *ice, uint32_t count = (sc) ? sc->count : 0; count *= draw->instance_count ? draw->instance_count : 1; - trace_intel_end_draw(&batch->trace, count); + trace_intel_end_draw(&batch->trace, count, 0, 0); } static void @@ -8769,7 +8769,7 @@ iris_upload_indirect_render_state(struct iris_context *ice, uint32_t count = (sc) ? sc->count : 0; count *= draw->instance_count ? draw->instance_count : 1; - trace_intel_end_draw(&batch->trace, count); + trace_intel_end_draw(&batch->trace, count, 0, 0); #else unreachable("Unsupported path"); #endif /* GFX_VERx10 >= 125 */ @@ -8955,7 +8955,7 @@ iris_upload_indirect_shader_render_state(struct iris_context *ice, uint32_t count = (sc) ? sc->count : 0; count *= draw->instance_count ? draw->instance_count : 1; - trace_intel_end_draw(&batch->trace, count); + trace_intel_end_draw(&batch->trace, count, 0, 0); } static void @@ -9129,7 +9129,7 @@ iris_upload_compute_walker(struct iris_context *ice, } } - trace_intel_end_compute(&batch->trace, grid->grid[0], grid->grid[1], grid->grid[2]); + trace_intel_end_compute(&batch->trace, grid->grid[0], grid->grid[1], grid->grid[2], 0); } #else /* #if GFX_VERx10 >= 125 */ @@ -9279,7 +9279,7 @@ iris_upload_gpgpu_walker(struct iris_context *ice, iris_emit_cmd(batch, GENX(MEDIA_STATE_FLUSH), msf); - trace_intel_end_compute(&batch->trace, grid->grid[0], grid->grid[1], grid->grid[2]); + trace_intel_end_compute(&batch->trace, grid->grid[0], grid->grid[1], grid->grid[2], 0); } #endif /* #if GFX_VERx10 >= 125 */ diff --git a/src/intel/ds/intel_tracepoints.py b/src/intel/ds/intel_tracepoints.py index 67cd0e29fa1..bbe8347d9fc 100644 --- a/src/intel/ds/intel_tracepoints.py +++ b/src/intel/ds/intel_tracepoints.py @@ -52,6 +52,15 @@ def define_tracepoints(args): global intel_default_tps if tp_default_enabled: intel_default_tps.append(name) + + # Preprocess arguments to handle display_as_hex + processed_args = [] + for arg in tp_args: + # Manually handle display_as_hex by modifying the format + if "hash" in arg.var: + arg = Arg(type=arg.type, var=arg.var, c_format='%#x') # Convert to hex format + processed_args.append(arg) + Tracepoint('intel_begin_{0}'.format(name), toggle_name=name, tp_perfetto='intel_ds_begin_{0}'.format(name), @@ -66,7 +75,7 @@ def define_tracepoints(args): tp_flags.append('INTEL_DS_TRACEPOINT_FLAG_END_OF_PIPE') Tracepoint('intel_end_{0}'.format(name), toggle_name=name, - args=tp_args, + args=processed_args, tp_struct=tp_struct, tp_perfetto='intel_ds_end_{0}'.format(name), tp_print=tp_print, @@ -151,25 +160,43 @@ def define_tracepoints(args): # Various draws/dispatch, Anv & Iris begin_end_tp('draw', - tp_args=[Arg(type='uint32_t', var='count', c_format='%u')]) + tp_args=[Arg(type='uint32_t', var='count', c_format='%u'), + Arg(type='uint32_t', var='vs_hash', c_format='%u'), + Arg(type='uint32_t', var='fs_hash', c_format='%u')]) begin_end_tp('draw_multi', - tp_args=[Arg(type='uint32_t', var='count', c_format='%u'),]) + tp_args=[Arg(type='uint32_t', var='count', c_format='%u'), + Arg(type='uint32_t', var='vs_hash', c_format='%u'), + Arg(type='uint32_t', var='fs_hash', c_format='%u')]) begin_end_tp('draw_indexed', - tp_args=[Arg(type='uint32_t', var='count', c_format='%u'),]) + tp_args=[Arg(type='uint32_t', var='count', c_format='%u'), + Arg(type='uint32_t', var='vs_hash', c_format='%u'), + Arg(type='uint32_t', var='fs_hash', c_format='%u')]) begin_end_tp('draw_indexed_multi', - tp_args=[Arg(type='uint32_t', var='count', c_format='%u'),]) + tp_args=[Arg(type='uint32_t', var='count', c_format='%u'), + Arg(type='uint32_t', var='vs_hash', c_format='%u'), + Arg(type='uint32_t', var='fs_hash', c_format='%u')]) begin_end_tp('draw_indirect_byte_count', - tp_args=[Arg(type='uint32_t', var='instance_count', c_format='%u'),]) + tp_args=[Arg(type='uint32_t', var='instance_count', c_format='%u'), + Arg(type='uint32_t', var='vs_hash', c_format='%u'), + Arg(type='uint32_t', var='fs_hash', c_format='%u')]) begin_end_tp('draw_indirect', - tp_args=[Arg(type='uint32_t', var='draw_count', c_format='%u'),]) + tp_args=[Arg(type='uint32_t', var='draw_count', c_format='%u'), + Arg(type='uint32_t', var='vs_hash', c_format='%u'), + Arg(type='uint32_t', var='fs_hash', c_format='%u')]) begin_end_tp('draw_indexed_indirect', - tp_args=[Arg(type='uint32_t', var='draw_count', c_format='%u'),]) + tp_args=[Arg(type='uint32_t', var='draw_count', c_format='%u'), + Arg(type='uint32_t', var='vs_hash', c_format='%u'), + Arg(type='uint32_t', var='fs_hash', c_format='%u')]) begin_end_tp('draw_indirect_count', tp_args=[Arg(type='uint32_t', var='draw_count', c_format='%u', - is_indirect=True),]) + is_indirect=True), + Arg(type='uint32_t', var='vs_hash', c_format='%u'), + Arg(type='uint32_t', var='fs_hash', c_format='%u')]) begin_end_tp('draw_indexed_indirect_count', tp_args=[Arg(type='uint32_t', var='draw_count', c_format='%u', - is_indirect=True),]) + is_indirect=True), + Arg(type='uint32_t', var='vs_hash', c_format='%u'), + Arg(type='uint32_t', var='fs_hash', c_format='%u')]) begin_end_tp('draw_mesh', tp_args=[Arg(type='uint32_t', var='group_x', c_format='%u'), @@ -184,13 +211,15 @@ def define_tracepoints(args): begin_end_tp('compute', tp_args=[Arg(type='uint32_t', var='group_x', c_format='%u'), Arg(type='uint32_t', var='group_y', c_format='%u'), - Arg(type='uint32_t', var='group_z', c_format='%u'),], + Arg(type='uint32_t', var='group_z', c_format='%u'), + Arg(type='uint32_t', var='cs_hash', c_format='%u')], compute=True) begin_end_tp('compute_indirect', tp_args=[ArgStruct(type='VkDispatchIndirectCommand', var='size', - is_indirect=True, c_format="%ux%ux%u", - fields=['x', 'y', 'z'])], + is_indirect=True, c_format="%ux%ux%u", + fields=['x', 'y', 'z']), + Arg(type='uint32_t', var='cs_hash', c_format='%u')], compute=True) # Used to identify copies generated by utrace diff --git a/src/intel/vulkan/genX_cmd_compute.c b/src/intel/vulkan/genX_cmd_compute.c index 3e6b94b301f..ab5ffed366b 100644 --- a/src/intel/vulkan/genX_cmd_compute.c +++ b/src/intel/vulkan/genX_cmd_compute.c @@ -624,7 +624,8 @@ void genX(CmdDispatchBase)( if (cmd_buffer->state.rt.debug_marker_count == 0) { trace_intel_end_compute(&cmd_buffer->trace, - groupCountX, groupCountY, groupCountZ); + groupCountX, groupCountY, groupCountZ, + pipeline->source_hash); } } @@ -684,7 +685,8 @@ emit_unaligned_cs_walker( if (cmd_buffer->state.rt.debug_marker_count == 0) { trace_intel_end_compute(&cmd_buffer->trace, - groupCountX, groupCountY, groupCountZ); + groupCountX, groupCountY, groupCountZ, + pipeline->source_hash); } } @@ -789,7 +791,8 @@ genX(cmd_buffer_dispatch_indirect)(struct anv_cmd_buffer *cmd_buffer, if (cmd_buffer->state.rt.debug_marker_count == 0) { trace_intel_end_compute_indirect(&cmd_buffer->trace, - anv_address_utrace(indirect_addr)); + anv_address_utrace(indirect_addr), + pipeline->source_hash); } } diff --git a/src/intel/vulkan/genX_cmd_draw.c b/src/intel/vulkan/genX_cmd_draw.c index 00930d216a3..f72c6325b89 100644 --- a/src/intel/vulkan/genX_cmd_draw.c +++ b/src/intel/vulkan/genX_cmd_draw.c @@ -1125,7 +1125,9 @@ void genX(CmdDraw)( cmd_buffer_post_draw_wa(cmd_buffer, vertexCount, SEQUENTIAL); - trace_intel_end_draw(&cmd_buffer->trace, count); + trace_intel_end_draw(&cmd_buffer->trace, count, + pipeline->base.source_hashes[MESA_SHADER_VERTEX], + pipeline->base.source_hashes[MESA_SHADER_FRAGMENT]); } void genX(CmdDrawMultiEXT)( @@ -1180,7 +1182,9 @@ void genX(CmdDrawMultiEXT)( pVertexInfo[drawCount - 1].vertexCount, SEQUENTIAL); - trace_intel_end_draw_multi(&cmd_buffer->trace, count); + trace_intel_end_draw_multi(&cmd_buffer->trace, count, + pipeline->base.source_hashes[MESA_SHADER_VERTEX], + pipeline->base.source_hashes[MESA_SHADER_FRAGMENT]); } #else vk_foreach_multi_draw(draw, i, pVertexInfo, drawCount, stride) { @@ -1214,7 +1218,9 @@ void genX(CmdDrawMultiEXT)( pVertexInfo[drawCount - 1].vertexCount, SEQUENTIAL); - trace_intel_end_draw_multi(&cmd_buffer->trace, count); + trace_intel_end_draw_multi(&cmd_buffer->trace, count, + pipeline->base.source_hashes[MESA_SHADER_VERTEX], + pipeline->base.source_hashes[MESA_SHADER_FRAGMENT]); } #endif } @@ -1284,7 +1290,9 @@ void genX(CmdDrawIndexed)( cmd_buffer_post_draw_wa(cmd_buffer, indexCount, RANDOM); - trace_intel_end_draw_indexed(&cmd_buffer->trace, count); + trace_intel_end_draw_indexed(&cmd_buffer->trace, count, + pipeline->base.source_hashes[MESA_SHADER_VERTEX], + pipeline->base.source_hashes[MESA_SHADER_FRAGMENT]); } void genX(CmdDrawMultiIndexedEXT)( @@ -1355,7 +1363,9 @@ void genX(CmdDrawMultiIndexedEXT)( pIndexInfo[drawCount - 1].indexCount, RANDOM); - trace_intel_end_draw_indexed_multi(&cmd_buffer->trace, count); + trace_intel_end_draw_indexed_multi(&cmd_buffer->trace, count, + pipeline->base.source_hashes[MESA_SHADER_VERTEX], + pipeline->base.source_hashes[MESA_SHADER_FRAGMENT]); emitted = false; } } else { @@ -1393,7 +1403,9 @@ void genX(CmdDrawMultiIndexedEXT)( pIndexInfo[drawCount - 1].indexCount, RANDOM); - trace_intel_end_draw_indexed_multi(&cmd_buffer->trace, count); + trace_intel_end_draw_indexed_multi(&cmd_buffer->trace, count, + pipeline->base.source_hashes[MESA_SHADER_VERTEX], + pipeline->base.source_hashes[MESA_SHADER_FRAGMENT]); } } } else { @@ -1427,7 +1439,9 @@ void genX(CmdDrawMultiIndexedEXT)( pIndexInfo[drawCount - 1].indexCount, RANDOM); - trace_intel_end_draw_indexed_multi(&cmd_buffer->trace, count); + trace_intel_end_draw_indexed_multi(&cmd_buffer->trace, count, + pipeline->base.source_hashes[MESA_SHADER_VERTEX], + pipeline->base.source_hashes[MESA_SHADER_FRAGMENT]); } } #else @@ -1464,7 +1478,9 @@ void genX(CmdDrawMultiIndexedEXT)( pIndexInfo[drawCount - 1].indexCount, RANDOM); - trace_intel_end_draw_indexed_multi(&cmd_buffer->trace, count); + trace_intel_end_draw_indexed_multi(&cmd_buffer->trace, count, + pipeline->base.source_hashes[MESA_SHADER_VERTEX], + pipeline->base.source_hashes[MESA_SHADER_FRAGMENT]); } #endif } @@ -1584,7 +1600,9 @@ void genX(CmdDrawIndirectByteCountEXT)( cmd_buffer_post_draw_wa(cmd_buffer, 1, SEQUENTIAL); trace_intel_end_draw_indirect_byte_count(&cmd_buffer->trace, - instanceCount * pipeline->instance_multiplier); + instanceCount * pipeline->instance_multiplier, + pipeline->base.source_hashes[MESA_SHADER_VERTEX], + pipeline->base.source_hashes[MESA_SHADER_FRAGMENT]); } static void @@ -1878,6 +1896,8 @@ void genX(CmdDrawIndirect)( { ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer); ANV_FROM_HANDLE(anv_buffer, buffer, _buffer); + struct anv_graphics_pipeline *pipeline = + anv_pipeline_to_graphics(cmd_buffer->state.gfx.base.pipeline); if (anv_batch_has_error(&cmd_buffer->batch)) return; @@ -1915,7 +1935,9 @@ void genX(CmdDrawIndirect)( stride, drawCount, false /* indexed */); } - trace_intel_end_draw_indirect(&cmd_buffer->trace, drawCount); + trace_intel_end_draw_indirect(&cmd_buffer->trace, drawCount, + pipeline->base.source_hashes[MESA_SHADER_VERTEX], + pipeline->base.source_hashes[MESA_SHADER_FRAGMENT]); } void genX(CmdDrawIndexedIndirect)( @@ -1927,6 +1949,8 @@ void genX(CmdDrawIndexedIndirect)( { ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer); ANV_FROM_HANDLE(anv_buffer, buffer, _buffer); + struct anv_graphics_pipeline *pipeline = + anv_pipeline_to_graphics(cmd_buffer->state.gfx.base.pipeline); if (anv_batch_has_error(&cmd_buffer->batch)) return; @@ -1964,7 +1988,9 @@ void genX(CmdDrawIndexedIndirect)( stride, drawCount, true /* indexed */); } - trace_intel_end_draw_indexed_indirect(&cmd_buffer->trace, drawCount); + trace_intel_end_draw_indexed_indirect(&cmd_buffer->trace, drawCount, + pipeline->base.source_hashes[MESA_SHADER_VERTEX], + pipeline->base.source_hashes[MESA_SHADER_FRAGMENT]); } #define MI_PREDICATE_SRC0 0x2400 @@ -2127,6 +2153,8 @@ void genX(CmdDrawIndirectCount)( ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer); ANV_FROM_HANDLE(anv_buffer, buffer, _buffer); ANV_FROM_HANDLE(anv_buffer, count_buffer, _countBuffer); + struct anv_graphics_pipeline *pipeline = + anv_pipeline_to_graphics(cmd_buffer->state.gfx.base.pipeline); if (anv_batch_has_error(&cmd_buffer->batch)) return; @@ -2169,7 +2197,9 @@ void genX(CmdDrawIndirectCount)( } trace_intel_end_draw_indirect_count(&cmd_buffer->trace, - anv_address_utrace(count_address)); + anv_address_utrace(count_address), + pipeline->base.source_hashes[MESA_SHADER_VERTEX], + pipeline->base.source_hashes[MESA_SHADER_FRAGMENT]); } void genX(CmdDrawIndexedIndirectCount)( @@ -2184,6 +2214,8 @@ void genX(CmdDrawIndexedIndirectCount)( ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer); ANV_FROM_HANDLE(anv_buffer, buffer, _buffer); ANV_FROM_HANDLE(anv_buffer, count_buffer, _countBuffer); + struct anv_graphics_pipeline *pipeline = + anv_pipeline_to_graphics(cmd_buffer->state.gfx.base.pipeline); if (anv_batch_has_error(&cmd_buffer->batch)) return; @@ -2226,7 +2258,9 @@ void genX(CmdDrawIndexedIndirectCount)( } trace_intel_end_draw_indexed_indirect_count(&cmd_buffer->trace, - anv_address_utrace(count_address)); + anv_address_utrace(count_address), + pipeline->base.source_hashes[MESA_SHADER_VERTEX], + pipeline->base.source_hashes[MESA_SHADER_FRAGMENT]); } diff --git a/src/intel/vulkan_hasvk/genX_cmd_buffer.c b/src/intel/vulkan_hasvk/genX_cmd_buffer.c index 5191d35a639..56abe110e02 100644 --- a/src/intel/vulkan_hasvk/genX_cmd_buffer.c +++ b/src/intel/vulkan_hasvk/genX_cmd_buffer.c @@ -3609,7 +3609,7 @@ void genX(CmdDraw)( update_dirty_vbs_for_gfx8_vb_flush(cmd_buffer, SEQUENTIAL); - trace_intel_end_draw(&cmd_buffer->trace, count); + trace_intel_end_draw(&cmd_buffer->trace, count, 0, 0); } void genX(CmdDrawMultiEXT)( @@ -3660,7 +3660,7 @@ void genX(CmdDrawMultiEXT)( update_dirty_vbs_for_gfx8_vb_flush(cmd_buffer, SEQUENTIAL); - trace_intel_end_draw_multi(&cmd_buffer->trace, count); + trace_intel_end_draw_multi(&cmd_buffer->trace, count, 0, 0); } void genX(CmdDrawIndexed)( @@ -3715,7 +3715,7 @@ void genX(CmdDrawIndexed)( update_dirty_vbs_for_gfx8_vb_flush(cmd_buffer, RANDOM); - trace_intel_end_draw_indexed(&cmd_buffer->trace, count); + trace_intel_end_draw_indexed(&cmd_buffer->trace, count, 0, 0); } void genX(CmdDrawMultiIndexedEXT)( @@ -3825,7 +3825,7 @@ void genX(CmdDrawMultiIndexedEXT)( update_dirty_vbs_for_gfx8_vb_flush(cmd_buffer, RANDOM); - trace_intel_end_draw_indexed_multi(&cmd_buffer->trace, count); + trace_intel_end_draw_indexed_multi(&cmd_buffer->trace, count, 0, 0); } /* Auto-Draw / Indirect Registers */ @@ -3906,7 +3906,7 @@ void genX(CmdDrawIndirectByteCountEXT)( update_dirty_vbs_for_gfx8_vb_flush(cmd_buffer, SEQUENTIAL); trace_intel_end_draw_indirect_byte_count(&cmd_buffer->trace, - instanceCount * pipeline->instance_multiplier); + instanceCount * pipeline->instance_multiplier, 0, 0); #endif /* GFX_VERx10 >= 75 */ } @@ -4004,7 +4004,7 @@ void genX(CmdDrawIndirect)( offset += stride; } - trace_intel_end_draw_indirect(&cmd_buffer->trace, drawCount); + trace_intel_end_draw_indirect(&cmd_buffer->trace, drawCount, 0, 0); } void genX(CmdDrawIndexedIndirect)( @@ -4062,7 +4062,7 @@ void genX(CmdDrawIndexedIndirect)( offset += stride; } - trace_intel_end_draw_indexed_indirect(&cmd_buffer->trace, drawCount); + trace_intel_end_draw_indexed_indirect(&cmd_buffer->trace, drawCount, 0, 0); } static struct mi_value @@ -4233,7 +4233,7 @@ void genX(CmdDrawIndirectCount)( mi_value_unref(&b, max); trace_intel_end_draw_indirect_count(&cmd_buffer->trace, - anv_address_utrace(count_address)); + anv_address_utrace(count_address), 0, 0); } void genX(CmdDrawIndexedIndirectCount)( @@ -4304,7 +4304,7 @@ void genX(CmdDrawIndexedIndirectCount)( mi_value_unref(&b, max); trace_intel_end_draw_indexed_indirect_count(&cmd_buffer->trace, - anv_address_utrace(count_address)); + anv_address_utrace(count_address), 0, 0); } void genX(CmdBeginTransformFeedbackEXT)( @@ -4637,7 +4637,8 @@ void genX(CmdDispatchBase)( groupCountY, groupCountZ); trace_intel_end_compute(&cmd_buffer->trace, - groupCountX, groupCountY, groupCountZ); + groupCountX, groupCountY, groupCountZ, + 0); } #define GPGPU_DISPATCHDIMX 0x2500 @@ -4745,8 +4746,7 @@ void genX(CmdDispatchIndirect)( #endif emit_cs_walker(cmd_buffer, pipeline, true, prog_data, 0, 0, 0); - - trace_intel_end_compute(&cmd_buffer->trace, 0, 0, 0); + trace_intel_end_compute(&cmd_buffer->trace, 0, 0, 0, 0); } static void