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aco: use non-sequential addressing

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fossil-db (GFX10.3):
Totals from 70493 (50.57% of 139391) affected shaders:
SGPRs: 4232624 -> 4231808 (-0.02%); split: -0.09%, +0.07%
VGPRs: 2831772 -> 2764740 (-2.37%); split: -2.53%, +0.17%
CodeSize: 225584412 -> 225048740 (-0.24%); split: -0.44%, +0.21%
MaxWaves: 875319 -> 878837 (+0.40%); split: +0.44%, -0.04%
Instrs: 43157803 -> 42496421 (-1.53%); split: -1.54%, +0.01%
Cycles: 1656380132 -> 1641532056 (-0.90%); split: -0.94%, +0.04%

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8523>
This commit is contained in:
Rhys Perry
2021-01-14 19:58:13 +00:00
committed by Marge Bot
parent faf3e9a27f
commit c353895c92
4 changed files with 68 additions and 30 deletions
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src/amd/compiler/aco_validate.cpp
+10 -3
View File
@@ -436,7 +436,7 @@ bool validate_ir(Program* program)
break;
}
case Format::MIMG: {
check(instr->operands.size() == 4, "MIMG instructions must have 4 operands", instr.get());
check(instr->operands.size() >= 4, "MIMG instructions must have at least 4 operands", instr.get());
check(instr->operands[0].hasRegClass() && (instr->operands[0].regClass() == s4 || instr->operands[0].regClass() == s8),
"MIMG operands[0] (resource constant) must be in 4 or 8 SGPRs", instr.get());
if (instr->operands[1].hasRegClass())
@@ -447,8 +447,15 @@ bool validate_ir(Program* program)
check(instr->definitions.empty() || (instr->definitions[0].regClass() == instr->operands[2].regClass() || is_cmpswap),
"MIMG operands[2] (VDATA) must be the same as definitions[0] for atomics and TFE/LWE loads", instr.get());
}
check(instr->operands[3].hasRegClass() && instr->operands[3].regClass().type() == RegType::vgpr,
"MIMG operands[3] (VADDR) must be VGPR", instr.get());
check(instr->operands.size() == 4 || program->chip_class >= GFX10, "NSA is only supported on GFX10+", instr.get());
for (unsigned i = 3; i < instr->operands.size(); i++) {
if (instr->operands.size() == 4) {
check(instr->operands[i].hasRegClass() && instr->operands[i].regClass().type() == RegType::vgpr,
"MIMG operands[3] (VADDR) must be VGPR", instr.get());
} else {
check(instr->operands[i].regClass() == v1, "MIMG VADDR must be v1 if NSA is used", instr.get());
}
}
check(instr->definitions.empty() || (instr->definitions[0].isTemp() && instr->definitions[0].regClass().type() == RegType::vgpr),
"MIMG definitions[0] (VDATA) must be VGPR", instr.get());
break;