diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c
index 285c0d5fc69..fa6cc45083b 100644
--- a/src/amd/vulkan/si_cmd_buffer.c
+++ b/src/amd/vulkan/si_cmd_buffer.c
@@ -593,7 +593,6 @@ si_emit_graphics(struct radv_device *device, struct radeon_cmdbuf *cs)
 
    if (physical_device->rad_info.gfx_level >= GFX11) {
       radeon_set_context_reg(cs, R_028C54_PA_SC_BINNER_CNTL_2, 0);
-      radeon_set_context_reg(cs, R_028620_PA_RATE_CNTL, S_028620_VERTEX_RATE(2) | S_028620_PRIM_RATE(1));
 
       uint64_t rb_mask = BITFIELD64_MASK(physical_device->rad_info.max_render_backends);
 
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index 1147412ebb3..3a4879d381c 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -5975,8 +5975,6 @@ static void gfx10_init_gfx_preamble_state(struct si_context *sctx, bool uses_reg
                       S_028410_COLOR_RD_POLICY(V_028410_CACHE_NOA_GFX10)) |
                   S_028410_DCC_RD_POLICY(meta_read_policy));
 
-   if (sctx->gfx_level >= GFX11)
-      si_pm4_set_reg(pm4, R_028620_PA_RATE_CNTL, S_028620_VERTEX_RATE(2) | S_028620_PRIM_RATE(1));
    if (sctx->gfx_level >= GFX10_3)
       si_pm4_set_reg(pm4, R_028750_SX_PS_DOWNCONVERT_CONTROL, 0xff);