From c2f4d3d139763a2fdd792bb7e00d47f32588b479 Mon Sep 17 00:00:00 2001 From: Zan Dobersek Date: Fri, 14 Mar 2025 11:12:13 +0100 Subject: [PATCH] ir3: fix display of dot-product instructions For dp2acc and dp4acc, don't display the derived NOP value by default, but do display repeat flags for source registers. When the nop encoding condition is met, the derived NOP value should be shown, mirroring what the base cat3 instruction specification does. Signed-off-by: Zan Dobersek Reviewed-by: Danylo Piliaiev Reviewed-by: Job Noorman Part-of: --- src/freedreno/ir3/tests/disasm.c | 1 + src/freedreno/isa/ir3-cat3.xml | 8 +++++++- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/src/freedreno/ir3/tests/disasm.c b/src/freedreno/ir3/tests/disasm.c index 58d83240e9c..1c18dfecea2 100644 --- a/src/freedreno/ir3/tests/disasm.c +++ b/src/freedreno/ir3/tests/disasm.c @@ -137,6 +137,7 @@ static const struct test { /* custom test with qcom_dot8 function from cl_qcom_dot_product8 */ INSTR_6XX(66818c02_0002e003, "(sat)(nop3) dp2acc.mixed.low r0.z, r0.w, r0.w, r0.z"), /* (nop3) dp2acc (sat)r0.z, (signed)(low)(r)r0.w, (low)(r)r0.w, r0.z */ INSTR_6XX(6681c802_8002a003, "(nop3) dp4acc.unsigned.low r0.z, r0.w, r0.w, (neg)r0.z"), /* (nop3) dp4acc r0.z, (unsigned)(r)r0.w, (r)r0.w, (neg)r0.z */ + INSTR_6XX(7681c002_00002002, "(sy)dp4acc.unsigned.low r0.z, r0.z, r0.w, r0.x"), INSTR_7XX(61808000_04020400, "madsh.m16 r0.x, (last)r0.x, r0.y, (last)r0.z"), INSTR_7XX(64838806_04088406, "(nop3) sel.b32 r1.z, (last)r1.z, r1.w, (last)r2.x"), diff --git a/src/freedreno/isa/ir3-cat3.xml b/src/freedreno/isa/ir3-cat3.xml index 457d14bacfa..9d6b7b760dc 100644 --- a/src/freedreno/isa/ir3-cat3.xml +++ b/src/freedreno/isa/ir3-cat3.xml @@ -344,8 +344,14 @@ SOFTWARE. + + + {SY}{SS}{JP}{SAT}(nop{NOP}) {UL}{NAME}{SRC_SIGN}{SRC_PACK} {DST}, {SRC1}, {SRC2}, {SRC3_NEG}{SRC3_R}{SRC3} + + + - {SY}{SS}{JP}{SAT}(nop{NOP}) {UL}{NAME}{SRC_SIGN}{SRC_PACK} {DST}, {SRC1}, {SRC2}, {SRC3_NEG}{SRC3} + {SY}{SS}{JP}{SAT}{UL}{NAME}{SRC_SIGN}{SRC_PACK} {DST}, {SRC1_R}{SRC1}, {SRC2_R}{SRC2}, {SRC3_NEG}{SRC3_R}{SRC3}