From c2d57f55a83fc6d9e418348f1f9a7a4c829327ba Mon Sep 17 00:00:00 2001 From: Rhys Perry Date: Thu, 28 Jan 2021 14:33:04 +0000 Subject: [PATCH] radv: relax shared alignment requirements in mem_vectorize_callback MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit fossil-db (GFX10.3): Totals from 13 (0.01% of 139391) affected shaders: CodeSize: 241316 -> 238684 (-1.09%) Instrs: 42251 -> 41912 (-0.80%); split: -0.81%, +0.01% Cycles: 1991192 -> 1974668 (-0.83%); split: -0.83%, +0.00% VMEM: 4067 -> 4102 (+0.86%) SMEM: 569 -> 578 (+1.58%) SClause: 848 -> 858 (+1.18%) Copies: 3077 -> 2992 (-2.76%); split: -3.12%, +0.36% Signed-off-by: Rhys Perry Reviewed-by: Daniel Schürmann Part-of: --- src/amd/vulkan/radv_pipeline.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 8eeb25d6d33..7c9e807e973 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -3081,8 +3081,10 @@ mem_vectorize_callback(unsigned align_mul, unsigned align_offset, FALLTHROUGH; case nir_intrinsic_load_shared: case nir_intrinsic_store_shared: - if (bit_size * num_components > 64) /* 96 and 128 bit loads require 128 bit alignment and are split otherwise */ + if (bit_size * num_components == 96) /* 96 bit loads require 128 bit alignment and are split otherwise */ return align % 16 == 0; + else if (bit_size * num_components == 128) /* 128 bit loads require 64 bit alignment and are split otherwise */ + return align % 8 == 0; else return align % (bit_size == 8 ? 2 : 4) == 0; default: