From c22444ebccfc4ababbec0cc05c0353cbf2767841 Mon Sep 17 00:00:00 2001 From: Danylo Piliaiev Date: Wed, 24 Aug 2022 14:52:50 +0300 Subject: [PATCH] freedreno: Add all variable magic regs to device-info tables There are more magic regs which have different values between GPU subgenerations than we specified. The updated list and values where obtained by using libwrapfake with v631 blob and dEQP-VK.draw.renderpass.basic_draw.draw.triangle_list.1 vk cts test. Signed-off-by: Danylo Piliaiev Part-of: --- src/freedreno/common/freedreno_dev_info.h | 11 +- src/freedreno/common/freedreno_devices.py | 156 +++++++++++++++++----- 2 files changed, 132 insertions(+), 35 deletions(-) diff --git a/src/freedreno/common/freedreno_dev_info.h b/src/freedreno/common/freedreno_dev_info.h index 1b1188f0afb..3e3682ddcfa 100644 --- a/src/freedreno/common/freedreno_dev_info.h +++ b/src/freedreno/common/freedreno_dev_info.h @@ -146,9 +146,18 @@ struct fd_dev_info { bool lrz_track_quirk; struct { - uint32_t RB_DBG_ECO_CNTL_blit; uint32_t PC_POWER_CNTL; uint32_t TPL1_DBG_ECO_CNTL; + uint32_t GRAS_DBG_ECO_CNTL; + uint32_t SP_CHICKEN_BITS; + uint32_t UCHE_CLIENT_PF; + uint32_t PC_MODE_CNTL; + uint32_t SP_DBG_ECO_CNTL; + uint32_t RB_DBG_ECO_CNTL_blit; + uint32_t HLSQ_DBG_ECO_CNTL; + uint32_t RB_UNKNOWN_8E01; + uint32_t VPC_DBG_ECO_CNTL; + uint32_t UCHE_UNKNOWN_0E12; } magic; } a6xx; }; diff --git a/src/freedreno/common/freedreno_devices.py b/src/freedreno/common/freedreno_devices.py index e877744853a..00ecf11d593 100644 --- a/src/freedreno/common/freedreno_devices.py +++ b/src/freedreno/common/freedreno_devices.py @@ -108,8 +108,7 @@ class A6xxGPUInfo(GPUInfo): into distinct sub-generations. The template parameter avoids duplication of parameters that are unique to the sub-generation. """ - def __init__(self, template, num_sp_cores, num_ccu, - RB_DBG_ECO_CNTL_blit, PC_POWER_CNTL): + def __init__(self, template, num_sp_cores, num_ccu, magic_regs): super().__init__(gmem_align_w = 16, gmem_align_h = 4, tile_align_w = 32, tile_align_h = 32, tile_max_w = 1024, # max_bitfield_val(5, 0, 5) @@ -126,13 +125,9 @@ class A6xxGPUInfo(GPUInfo): self.a6xx = Struct() self.a6xx.magic = Struct() - for name, val in template["magic"].items(): + for name, val in magic_regs.items(): setattr(self.a6xx.magic, name, val) - # Various "magic" register values: - self.a6xx.magic.RB_DBG_ECO_CNTL_blit = RB_DBG_ECO_CNTL_blit - self.a6xx.magic.PC_POWER_CNTL = PC_POWER_CNTL - # Things that earlier gens have and later gens remove, provide # defaults here and let them be overridden by sub-gen template: self.a6xx.has_cp_reg_write = True @@ -210,9 +205,6 @@ a6xx_gen1 = dict( concurrent_resolve = True, indirect_draw_wfm_quirk = True, depth_bounds_require_depth_test_quirk = True, - magic = dict( - TPL1_DBG_ECO_CNTL = 0x100000, - ) ) # a640, a680: @@ -225,9 +217,6 @@ a6xx_gen2 = dict( indirect_draw_wfm_quirk = True, depth_bounds_require_depth_test_quirk = True, # TODO: check if true has_dp2acc = False, # TODO: check if true - magic = dict( - TPL1_DBG_ECO_CNTL = 0, - ), ) # a650: @@ -248,10 +237,6 @@ a6xx_gen3 = dict( has_lrz_dir_tracking = True, enable_lrz_fast_clear = True, lrz_track_quirk = True, - magic = dict( - # this seems to be a chicken bit that fixes cubic filtering: - TPL1_DBG_ECO_CNTL = 0x1000000, - ), ) # a635, a660: @@ -276,9 +261,6 @@ a6xx_gen4 = dict( has_dp4acc = True, enable_lrz_fast_clear = True, has_lrz_dir_tracking = True, - magic = dict( - TPL1_DBG_ECO_CNTL = 0x5008000, - ), ) add_gpus([ @@ -286,13 +268,46 @@ add_gpus([ GPUId(616), GPUId(618), GPUId(619), + ], A6xxGPUInfo( + a6xx_gen1, + num_sp_cores = 1, + num_ccu = 1, + magic_regs = dict( + PC_POWER_CNTL = 0, + TPL1_DBG_ECO_CNTL = 0x00108000, + GRAS_DBG_ECO_CNTL = 0x00000880, + SP_CHICKEN_BITS = 0x00000430, + UCHE_CLIENT_PF = 0x00000004, + PC_MODE_CNTL = 0x1f, + SP_DBG_ECO_CNTL = 0x0, + RB_DBG_ECO_CNTL_blit = 0x04100000, + HLSQ_DBG_ECO_CNTL = 0x00080000, + RB_UNKNOWN_8E01 = 0x00000001, + VPC_DBG_ECO_CNTL = 0x0, + UCHE_UNKNOWN_0E12 = 0x00000001 + ) + )) + +add_gpus([ GPUId(620), ], A6xxGPUInfo( a6xx_gen1, num_sp_cores = 1, num_ccu = 1, - RB_DBG_ECO_CNTL_blit = 0x00100000, - PC_POWER_CNTL = 0, + magic_regs = dict( + PC_POWER_CNTL = 0, + TPL1_DBG_ECO_CNTL = 0x01008000, + GRAS_DBG_ECO_CNTL = 0x0, + SP_CHICKEN_BITS = 0x00000400, + UCHE_CLIENT_PF = 0x00000004, + PC_MODE_CNTL = 0x1f, + SP_DBG_ECO_CNTL = 0x01000000, + RB_DBG_ECO_CNTL_blit = 0x04100000, + HLSQ_DBG_ECO_CNTL = 0x0, + RB_UNKNOWN_8E01 = 0x0, + VPC_DBG_ECO_CNTL = 0x02000000, + UCHE_UNKNOWN_0E12 = 0x00000001 + ) )) add_gpus([ @@ -301,8 +316,20 @@ add_gpus([ a6xx_gen1, num_sp_cores = 2, num_ccu = 2, - RB_DBG_ECO_CNTL_blit = 0x01000000, - PC_POWER_CNTL = 1, + magic_regs = dict( + PC_POWER_CNTL = 1, + TPL1_DBG_ECO_CNTL = 0x00108000, + GRAS_DBG_ECO_CNTL = 0x00000880, + SP_CHICKEN_BITS = 0x00001430, + UCHE_CLIENT_PF = 0x00000004, + PC_MODE_CNTL = 0x1f, + SP_DBG_ECO_CNTL = 0x0, + RB_DBG_ECO_CNTL_blit = 0x04100000, + HLSQ_DBG_ECO_CNTL = 0x00080000, + RB_UNKNOWN_8E01 = 0x00000001, + VPC_DBG_ECO_CNTL = 0x0, + UCHE_UNKNOWN_0E12 = 0x10000001 + ) )) add_gpus([ @@ -311,8 +338,20 @@ add_gpus([ a6xx_gen2, num_sp_cores = 2, num_ccu = 2, - RB_DBG_ECO_CNTL_blit = 0x00100000, - PC_POWER_CNTL = 1, + magic_regs = dict( + PC_POWER_CNTL = 1, + TPL1_DBG_ECO_CNTL = 0x00008000, + GRAS_DBG_ECO_CNTL = 0x0, + SP_CHICKEN_BITS = 0x00000420, + UCHE_CLIENT_PF = 0x00000004, + PC_MODE_CNTL = 0x1f, + SP_DBG_ECO_CNTL = 0x0, + RB_DBG_ECO_CNTL_blit = 0x04100000, + HLSQ_DBG_ECO_CNTL = 0x0, + RB_UNKNOWN_8E01 = 0x00000001, + VPC_DBG_ECO_CNTL = 0x02000000, + UCHE_UNKNOWN_0E12 = 0x00000001 + ) )) add_gpus([ @@ -321,8 +360,20 @@ add_gpus([ a6xx_gen2, num_sp_cores = 4, num_ccu = 4, - RB_DBG_ECO_CNTL_blit = 0x04100000, - PC_POWER_CNTL = 3, + magic_regs = dict( + PC_POWER_CNTL = 3, + TPL1_DBG_ECO_CNTL = 0x00108000, + GRAS_DBG_ECO_CNTL = 0x0, + SP_CHICKEN_BITS = 0x00001430, + UCHE_CLIENT_PF = 0x00000004, + PC_MODE_CNTL = 0x1f, + SP_DBG_ECO_CNTL = 0x0, + RB_DBG_ECO_CNTL_blit = 0x04100000, + HLSQ_DBG_ECO_CNTL = 0x0, + RB_UNKNOWN_8E01 = 0x00000001, + VPC_DBG_ECO_CNTL = 0x02000000, + UCHE_UNKNOWN_0E12 = 0x00000001 + ) )) add_gpus([ @@ -331,8 +382,21 @@ add_gpus([ a6xx_gen3, num_sp_cores = 3, num_ccu = 3, - RB_DBG_ECO_CNTL_blit = 0x04100000, - PC_POWER_CNTL = 2, + magic_regs = dict( + PC_POWER_CNTL = 2, + # this seems to be a chicken bit that fixes cubic filtering: + TPL1_DBG_ECO_CNTL = 0x01008000, + GRAS_DBG_ECO_CNTL = 0x0, + SP_CHICKEN_BITS = 0x00001400, + UCHE_CLIENT_PF = 0x00000004, + PC_MODE_CNTL = 0x1f, + SP_DBG_ECO_CNTL = 0x01000000, + RB_DBG_ECO_CNTL_blit = 0x04100000, + HLSQ_DBG_ECO_CNTL = 0x0, + RB_UNKNOWN_8E01 = 0x0, + VPC_DBG_ECO_CNTL = 0x02000000, + UCHE_UNKNOWN_0E12 = 0x00000001 + ) )) add_gpus([ @@ -345,8 +409,20 @@ add_gpus([ a6xx_gen4, num_sp_cores = 2, num_ccu = 2, - RB_DBG_ECO_CNTL_blit = 0x00100000, - PC_POWER_CNTL = 1, + magic_regs = dict( + PC_POWER_CNTL = 1, + TPL1_DBG_ECO_CNTL = 0x05008000, + GRAS_DBG_ECO_CNTL = 0x0, + SP_CHICKEN_BITS = 0x00001400, + UCHE_CLIENT_PF = 0x00000084, + PC_MODE_CNTL = 0x1f, + SP_DBG_ECO_CNTL = 0x00000006, + RB_DBG_ECO_CNTL_blit = 0x04100000, + HLSQ_DBG_ECO_CNTL = 0x0, + RB_UNKNOWN_8E01 = 0x0, + VPC_DBG_ECO_CNTL = 0x02000000, + UCHE_UNKNOWN_0E12 = 0x00000001 + ) )) add_gpus([ @@ -355,8 +431,20 @@ add_gpus([ a6xx_gen4, num_sp_cores = 3, num_ccu = 3, - RB_DBG_ECO_CNTL_blit = 0x04100000, - PC_POWER_CNTL = 2, + magic_regs = dict( + PC_POWER_CNTL = 2, + TPL1_DBG_ECO_CNTL = 0x05008000, + GRAS_DBG_ECO_CNTL = 0x0, + SP_CHICKEN_BITS = 0x00001400, + UCHE_CLIENT_PF = 0x00000084, + PC_MODE_CNTL = 0x1f, + SP_DBG_ECO_CNTL = 0x01000000, + RB_DBG_ECO_CNTL_blit = 0x04100000, + HLSQ_DBG_ECO_CNTL = 0x0, + RB_UNKNOWN_8E01 = 0x0, + VPC_DBG_ECO_CNTL = 0x02000000, + UCHE_UNKNOWN_0E12 = 0x00000001 + ) )) template = """\