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intel/fs/gfx20+: Fix surface state address on extended descriptors for NIR scratch intrinsics.

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The r0.5 thread payload register contains Surface State Offset bits
[27:6] as bits [31:10], so we need to shift the register right by 4 in
order to get the surface state offset expected in ExBSO mode, which is
the only extended descriptor encoding supported by the UGM shared
function for SS addressing on Xe2+.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29543>
This commit is contained in:
Francisco Jerez
2024-06-04 19:27:26 -07:00
committed by Marge Bot
parent 8bbad903a2
commit c1feccdd90
3 changed files with 11 additions and 0 deletions
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src/intel/compiler/brw_fs_nir.cpp
+4
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@@ -6740,6 +6740,8 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb,
fs_reg handle = component(ubld.vgrf(BRW_TYPE_UD), 0);
ubld.AND(handle, retype(brw_vec1_grf(0, 5), BRW_TYPE_UD),
brw_imm_ud(INTEL_MASK(31, 10)));
if (devinfo->ver >= 20)
ubld.SHR(handle, handle, brw_imm_ud(4));
srcs[SURFACE_LOGICAL_SRC_SURFACE] = brw_imm_ud(GFX125_NON_BINDLESS);
srcs[SURFACE_LOGICAL_SRC_SURFACE_HANDLE] = handle;
} else {
@@ -6800,6 +6802,8 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb,
fs_reg handle = component(ubld.vgrf(BRW_TYPE_UD), 0);
ubld.AND(handle, retype(brw_vec1_grf(0, 5), BRW_TYPE_UD),
brw_imm_ud(INTEL_MASK(31, 10)));
if (devinfo->ver >= 20)
ubld.SHR(handle, handle, brw_imm_ud(4));
srcs[SURFACE_LOGICAL_SRC_SURFACE] = brw_imm_ud(GFX125_NON_BINDLESS);
srcs[SURFACE_LOGICAL_SRC_SURFACE_HANDLE] = handle;
} else {