From c15b8329fdfcd635b04315dd3ded31768c0e2fc4 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Tapani=20P=C3=A4lli?= <tapani.palli@intel.com>
Date: Mon, 6 Oct 2025 14:04:46 +0300
Subject: [PATCH] anv: add cs stall for any pipe control on compute
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Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37715>
---
 src/intel/vulkan/genX_cmd_buffer.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c
index 7d1a87442ee..662ad03bb81 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -2500,6 +2500,16 @@ emit_pipe_control(struct anv_batch *batch,
       bits |= ANV_PIPE_HDC_PIPELINE_FLUSH_BIT;
 #endif
 
+   /* BSpec 47112 (xe), 56551 (xe2): Instruction_PIPE_CONTROL (ComputeCS):
+    * SW must follow below programming restrictions when programming
+    * PIPE_CONTROL command:
+    *
+    * "Command Streamer Stall Enable" must be always set.
+    * ...
+    */
+   if (batch->engine_class == INTEL_ENGINE_CLASS_COMPUTE)
+      bits |= ANV_PIPE_CS_STALL_BIT;
+
 #if GFX_VER < 12
    if (bits & ANV_PIPE_HDC_PIPELINE_FLUSH_BIT)
       bits |= ANV_PIPE_DATA_CACHE_FLUSH_BIT;