From c0397a42ce086db76e9cce760e63f4f80545b0de Mon Sep 17 00:00:00 2001 From: Mike Blumenkrantz Date: Wed, 2 Jun 2021 12:55:34 -0400 Subject: [PATCH] radv: pre-calc vertex buffer descriptor size on pipeline object util_bitcount has a nonzero cost, and calling it like this in a hotpath generates unnecessary overhead Reviewed-by: Samuel Pitoiset Part-of: --- src/amd/vulkan/radv_cmd_buffer.c | 6 ++---- src/amd/vulkan/radv_pipeline.c | 1 + src/amd/vulkan/radv_private.h | 2 +- 3 files changed, 4 insertions(+), 5 deletions(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 76f010773e1..37ee54d8103 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -1053,7 +1053,7 @@ radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer, struct radv_pipeline * radv_emit_shader_prefetch(cmd_buffer, pipeline->shaders[MESA_SHADER_VERTEX]); if (mask & RADV_PREFETCH_VBO_DESCRIPTORS) - si_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size); + si_cp_dma_prefetch(cmd_buffer, state->vb_va, pipeline->vb_desc_alloc_size); if (mask & RADV_PREFETCH_TCS) radv_emit_shader_prefetch(cmd_buffer, pipeline->shaders[MESA_SHADER_TESS_CTRL]); @@ -2837,11 +2837,10 @@ radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_ void *vb_ptr; unsigned desc_index = 0; uint32_t mask = pipeline->vb_desc_usage_mask; - uint32_t count = util_bitcount(mask); uint64_t va; /* allocate some descriptor state for vertex buffers */ - if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, &vb_offset, &vb_ptr)) + if (!radv_cmd_buffer_upload_alloc(cmd_buffer, pipeline->vb_desc_alloc_size, &vb_offset, &vb_ptr)) return; while (mask) { @@ -2924,7 +2923,6 @@ radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_ va); cmd_buffer->state.vb_va = va; - cmd_buffer->state.vb_size = count * 16; cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS; if (unlikely(cmd_buffer->device->trace_bo)) diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 3ff3161438d..4263a593531 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -5305,6 +5305,7 @@ radv_pipeline_init_vertex_input_state(struct radv_pipeline *pipeline, pipeline->use_per_attribute_vb_descs = info->vs.use_per_attribute_vb_descs; pipeline->vb_desc_usage_mask = info->vs.vb_desc_usage_mask; + pipeline->vb_desc_alloc_size = util_bitcount(pipeline->vb_desc_usage_mask) * 16; } static struct radv_shader_variant * diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index e0917f1b6ec..d98f8805f68 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/amd/vulkan/radv_private.h @@ -1342,7 +1342,6 @@ enum rgp_flush_bits { struct radv_cmd_state { /* Vertex descriptors */ uint64_t vb_va; - unsigned vb_size; bool predicating; uint64_t dirty; @@ -1730,6 +1729,7 @@ struct radv_pipeline { bool use_per_attribute_vb_descs; uint32_t vb_desc_usage_mask; + uint32_t vb_desc_alloc_size; uint32_t user_data_0[MESA_SHADER_STAGES]; union {