From c036736e2e5a3d389f0d62bdcf0ef6c97eacaf51 Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Mon, 24 Mar 2025 09:36:27 +0100 Subject: [PATCH] radv/video: rework command buffer emission This is much closer to RadeonSI and could be shared at some point. Signed-off-by: Samuel Pitoiset Part-of: --- src/amd/vulkan/radv_radeon_winsys.h | 7 - src/amd/vulkan/radv_video_enc.c | 579 +++++++++++++--------------- 2 files changed, 272 insertions(+), 314 deletions(-) diff --git a/src/amd/vulkan/radv_radeon_winsys.h b/src/amd/vulkan/radv_radeon_winsys.h index c5775e45b6f..422e5bfb1bf 100644 --- a/src/amd/vulkan/radv_radeon_winsys.h +++ b/src/amd/vulkan/radv_radeon_winsys.h @@ -328,13 +328,6 @@ radeon_emit(struct radeon_cmdbuf *cs, uint32_t value) cs->buf[cs->cdw++] = value; } -static inline void -radeon_emit_direct(struct radeon_cmdbuf *cs, uint32_t offset, uint32_t value) -{ - assert(offset < cs->reserved_dw); - cs->buf[offset] = value; -} - static inline void radeon_emit_array(struct radeon_cmdbuf *cs, const uint32_t *values, unsigned count) { diff --git a/src/amd/vulkan/radv_video_enc.c b/src/amd/vulkan/radv_video_enc.c index d2bdeed0947..5c45814e85c 100644 --- a/src/amd/vulkan/radv_video_enc.c +++ b/src/amd/vulkan/radv_video_enc.c @@ -429,13 +429,16 @@ radv_enc_code_se(struct radv_cmd_buffer *cmd_buffer, int value) radv_enc_code_ue(cmd_buffer, v); } -#define ENC_BEGIN \ - { \ - uint32_t begin = cs->cdw++; +#define RADEON_ENC_CS(value) (cmd_buffer->cs->buf[cmd_buffer->cs->cdw++] = (value)) -#define ENC_END \ - radeon_emit_direct(cs, begin, (cs->cdw - begin) * 4); \ - cmd_buffer->video.enc.total_task_size += cs->buf[begin]; \ +#define RADEON_ENC_BEGIN(cmd) \ + { \ + uint32_t *begin = &cmd_buffer->cs->buf[cmd_buffer->cs->cdw++]; \ + RADEON_ENC_CS(cmd) + +#define RADEON_ENC_END() \ + *begin = (&cmd_buffer->cs->buf[cmd_buffer->cs->cdw] - begin) * 4; \ + cmd_buffer->video.enc.total_task_size += *begin; \ } static void @@ -444,17 +447,18 @@ radv_enc_session_info(struct radv_cmd_buffer *cmd_buffer) struct radv_device *device = radv_cmd_buffer_device(cmd_buffer); const struct radv_physical_device *pdev = radv_device_physical(device); struct radeon_cmdbuf *cs = cmd_buffer->cs; - ENC_BEGIN; - radeon_emit(cs, pdev->vcn_enc_cmds.session_info); - radeon_emit(cs, pdev->encoder_interface_version); radv_cs_add_buffer(device->ws, cs, cmd_buffer->video.vid->sessionctx.mem->bo); + uint64_t va = radv_buffer_get_va(cmd_buffer->video.vid->sessionctx.mem->bo); va += cmd_buffer->video.vid->sessionctx.offset; - radeon_emit(cs, va >> 32); - radeon_emit(cs, va & 0xffffffff); - radeon_emit(cs, RENCODE_ENGINE_TYPE_ENCODE); - ENC_END; + + RADEON_ENC_BEGIN(pdev->vcn_enc_cmds.session_info); + RADEON_ENC_CS(pdev->encoder_interface_version); + RADEON_ENC_CS(va >> 32); + RADEON_ENC_CS(va & 0xffffffff); + RADEON_ENC_CS(RENCODE_ENGINE_TYPE_ENCODE); + RADEON_ENC_END(); } static void @@ -466,12 +470,11 @@ radv_enc_task_info(struct radv_cmd_buffer *cmd_buffer, bool feedback) struct radv_enc_state *enc = &cmd_buffer->video.enc; enc->task_id++; - ENC_BEGIN; - radeon_emit(cs, pdev->vcn_enc_cmds.task_info); + RADEON_ENC_BEGIN(pdev->vcn_enc_cmds.task_info); enc->p_task_size = &cs->buf[cs->cdw++]; - radeon_emit(cs, enc->task_id); - radeon_emit(cs, feedback ? 1 : 0); - ENC_END; + RADEON_ENC_CS(enc->task_id); + RADEON_ENC_CS(feedback ? 1 : 0); + RADEON_ENC_END(); } static void @@ -480,7 +483,6 @@ radv_enc_session_init(struct radv_cmd_buffer *cmd_buffer, const struct VkVideoEn struct radv_device *device = radv_cmd_buffer_device(cmd_buffer); const struct radv_physical_device *pdev = radv_device_physical(device); struct radv_video_session *vid = cmd_buffer->video.vid; - struct radeon_cmdbuf *cs = cmd_buffer->cs; unsigned alignment_w = 16; unsigned alignment_h = 16; if (vid->vk.op == VK_VIDEO_CODEC_OPERATION_ENCODE_H265_BIT_KHR) { @@ -494,23 +496,22 @@ radv_enc_session_init(struct radv_cmd_buffer *cmd_buffer, const struct VkVideoEn uint32_t padding_width = aligned_picture_width - w; uint32_t padding_height = aligned_picture_height - h; - ENC_BEGIN; - radeon_emit(cs, pdev->vcn_enc_cmds.session_init); - radeon_emit(cs, vid->enc_session.encode_standard); - radeon_emit(cs, aligned_picture_width); - radeon_emit(cs, aligned_picture_height); - radeon_emit(cs, padding_width); - radeon_emit(cs, padding_height); - radeon_emit(cs, vid->enc_session.pre_encode_mode); - radeon_emit(cs, vid->enc_session.pre_encode_chroma_enabled); + RADEON_ENC_BEGIN(pdev->vcn_enc_cmds.session_init); + RADEON_ENC_CS(vid->enc_session.encode_standard); + RADEON_ENC_CS(aligned_picture_width); + RADEON_ENC_CS(aligned_picture_height); + RADEON_ENC_CS(padding_width); + RADEON_ENC_CS(padding_height); + RADEON_ENC_CS(vid->enc_session.pre_encode_mode); + RADEON_ENC_CS(vid->enc_session.pre_encode_chroma_enabled); if (pdev->enc_hw_ver >= RADV_VIDEO_ENC_HW_3) { - radeon_emit(cs, 0); // slice output enabled. + RADEON_ENC_CS(0); // slice output enabled. } - radeon_emit(cs, vid->enc_session.display_remote); + RADEON_ENC_CS(vid->enc_session.display_remote); if (pdev->enc_hw_ver >= RADV_VIDEO_ENC_HW_4) { - radeon_emit(cs, 0); + RADEON_ENC_CS(0); } - ENC_END; + RADEON_ENC_END(); } static void @@ -518,12 +519,11 @@ radv_enc_layer_control(struct radv_cmd_buffer *cmd_buffer, const rvcn_enc_layer_ { struct radv_device *device = radv_cmd_buffer_device(cmd_buffer); const struct radv_physical_device *pdev = radv_device_physical(device); - struct radeon_cmdbuf *cs = cmd_buffer->cs; - ENC_BEGIN; - radeon_emit(cs, pdev->vcn_enc_cmds.layer_control); - radeon_emit(cs, rc_layer_control->max_num_temporal_layers); // max num temporal layesr - radeon_emit(cs, rc_layer_control->num_temporal_layers); // num temporal layers - ENC_END; + + RADEON_ENC_BEGIN(pdev->vcn_enc_cmds.layer_control); + RADEON_ENC_CS(rc_layer_control->max_num_temporal_layers); // max num temporal layesr + RADEON_ENC_CS(rc_layer_control->num_temporal_layers); // num temporal layers + RADEON_ENC_END(); } static void @@ -531,11 +531,10 @@ radv_enc_layer_select(struct radv_cmd_buffer *cmd_buffer, int tl_idx) { struct radv_device *device = radv_cmd_buffer_device(cmd_buffer); const struct radv_physical_device *pdev = radv_device_physical(device); - struct radeon_cmdbuf *cs = cmd_buffer->cs; - ENC_BEGIN; - radeon_emit(cs, pdev->vcn_enc_cmds.layer_select); - radeon_emit(cs, tl_idx); // temporal layer index - ENC_END; + + RADEON_ENC_BEGIN(pdev->vcn_enc_cmds.layer_select); + RADEON_ENC_CS(tl_idx); // temporal layer index + RADEON_ENC_END(); } static void @@ -543,17 +542,16 @@ radv_enc_slice_control(struct radv_cmd_buffer *cmd_buffer, const struct VkVideoE { struct radv_device *device = radv_cmd_buffer_device(cmd_buffer); const struct radv_physical_device *pdev = radv_device_physical(device); - struct radeon_cmdbuf *cs = cmd_buffer->cs; uint32_t num_mbs_in_slice; uint32_t width_in_mbs = DIV_ROUND_UP(enc_info->srcPictureResource.codedExtent.width, 16); uint32_t height_in_mbs = DIV_ROUND_UP(enc_info->srcPictureResource.codedExtent.height, 16); num_mbs_in_slice = width_in_mbs * height_in_mbs; - ENC_BEGIN; - radeon_emit(cs, pdev->vcn_enc_cmds.slice_control_h264); - radeon_emit(cs, RENCODE_H264_SLICE_CONTROL_MODE_FIXED_MBS); // slice control mode - radeon_emit(cs, num_mbs_in_slice); // num mbs per slice - ENC_END; + + RADEON_ENC_BEGIN(pdev->vcn_enc_cmds.slice_control_h264); + RADEON_ENC_CS(RENCODE_H264_SLICE_CONTROL_MODE_FIXED_MBS); // slice control mode + RADEON_ENC_CS(num_mbs_in_slice); // num mbs per slice + RADEON_ENC_END(); } static void @@ -561,7 +559,6 @@ radv_enc_spec_misc_h264(struct radv_cmd_buffer *cmd_buffer, const struct VkVideo { struct radv_device *device = radv_cmd_buffer_device(cmd_buffer); const struct radv_physical_device *pdev = radv_device_physical(device); - struct radeon_cmdbuf *cs = cmd_buffer->cs; const struct VkVideoEncodeH264PictureInfoKHR *h264_picture_info = vk_find_struct_const(enc_info->pNext, VIDEO_ENCODE_H264_PICTURE_INFO_KHR); const StdVideoEncodeH264PictureInfo *pic = h264_picture_info->pStdPictureInfo; @@ -569,26 +566,26 @@ radv_enc_spec_misc_h264(struct radv_cmd_buffer *cmd_buffer, const struct VkVideo vk_video_find_h264_enc_std_sps(&cmd_buffer->video.params->vk, pic->seq_parameter_set_id); const StdVideoH264PictureParameterSet *pps = vk_video_find_h264_enc_std_pps(&cmd_buffer->video.params->vk, pic->pic_parameter_set_id); - ENC_BEGIN; - radeon_emit(cs, pdev->vcn_enc_cmds.spec_misc_h264); - radeon_emit(cs, pps->flags.constrained_intra_pred_flag); // constrained_intra_pred_flag - radeon_emit(cs, pps->flags.entropy_coding_mode_flag); // cabac enable - radeon_emit(cs, 0); // cabac init idc - radeon_emit(cs, 1); // half pel enabled - radeon_emit(cs, 1); // quarter pel enabled - radeon_emit(cs, cmd_buffer->video.vid->vk.h264.profile_idc); // profile_idc - radeon_emit(cs, vk_video_get_h264_level(sps->level_idc)); + + RADEON_ENC_BEGIN(pdev->vcn_enc_cmds.spec_misc_h264); + RADEON_ENC_CS(pps->flags.constrained_intra_pred_flag); // constrained_intra_pred_flag + RADEON_ENC_CS(pps->flags.entropy_coding_mode_flag); // cabac enable + RADEON_ENC_CS(0); // cabac init idc + RADEON_ENC_CS(1); // half pel enabled + RADEON_ENC_CS(1); // quarter pel enabled + RADEON_ENC_CS(cmd_buffer->video.vid->vk.h264.profile_idc); // profile_idc + RADEON_ENC_CS(vk_video_get_h264_level(sps->level_idc)); if (pdev->enc_hw_ver >= RADV_VIDEO_ENC_HW_3) { bool b_pic_enabled = false; if (sps->pSequenceParameterSetVui) { b_pic_enabled = !!sps->pSequenceParameterSetVui->max_num_reorder_frames; } - radeon_emit(cs, b_pic_enabled); // v3 b_picture_enabled - radeon_emit(cs, pps->weighted_bipred_idc); // v3 weighted bipred idc + RADEON_ENC_CS(b_pic_enabled); // v3 b_picture_enabled + RADEON_ENC_CS(pps->weighted_bipred_idc); // v3 weighted bipred idc } - ENC_END; + RADEON_ENC_END(); } static void @@ -596,7 +593,6 @@ radv_enc_spec_misc_hevc(struct radv_cmd_buffer *cmd_buffer, const struct VkVideo { struct radv_device *device = radv_cmd_buffer_device(cmd_buffer); const struct radv_physical_device *pdev = radv_device_physical(device); - struct radeon_cmdbuf *cs = cmd_buffer->cs; const struct VkVideoEncodeH265PictureInfoKHR *h265_picture_info = vk_find_struct_const(enc_info->pNext, VIDEO_ENCODE_H265_PICTURE_INFO_KHR); const StdVideoEncodeH265PictureInfo *pic = h265_picture_info->pStdPictureInfo; @@ -606,20 +602,20 @@ radv_enc_spec_misc_hevc(struct radv_cmd_buffer *cmd_buffer, const struct VkVideo vk_video_find_h265_enc_std_sps(&cmd_buffer->video.params->vk, pic->pps_seq_parameter_set_id); const StdVideoH265PictureParameterSet *pps = vk_video_find_h265_enc_std_pps(&cmd_buffer->video.params->vk, pic->pps_pic_parameter_set_id); - ENC_BEGIN; - radeon_emit(cs, pdev->vcn_enc_cmds.spec_misc_hevc); - radeon_emit(cs, sps->log2_min_luma_coding_block_size_minus3); - radeon_emit(cs, !sps->flags.amp_enabled_flag); - radeon_emit(cs, sps->flags.strong_intra_smoothing_enabled_flag); - radeon_emit(cs, pps->flags.constrained_intra_pred_flag); - radeon_emit(cs, slice->flags.cabac_init_flag); - radeon_emit(cs, 1); // enc->enc_pic.hevc_spec_misc.half_pel_enabled - radeon_emit(cs, 1); // enc->enc_pic.hevc_spec_misc.quarter_pel_enabled + + RADEON_ENC_BEGIN(pdev->vcn_enc_cmds.spec_misc_hevc); + RADEON_ENC_CS(sps->log2_min_luma_coding_block_size_minus3); + RADEON_ENC_CS(!sps->flags.amp_enabled_flag); + RADEON_ENC_CS(sps->flags.strong_intra_smoothing_enabled_flag); + RADEON_ENC_CS(pps->flags.constrained_intra_pred_flag); + RADEON_ENC_CS(slice->flags.cabac_init_flag); + RADEON_ENC_CS(1); // enc->enc_pic.hevc_spec_misc.half_pel_enabled + RADEON_ENC_CS(1); // enc->enc_pic.hevc_spec_misc.quarter_pel_enabled if (pdev->enc_hw_ver >= RADV_VIDEO_ENC_HW_3) { - radeon_emit(cs, !pps->flags.transform_skip_enabled_flag); - radeon_emit(cs, pps->flags.cu_qp_delta_enabled_flag); + RADEON_ENC_CS(!pps->flags.transform_skip_enabled_flag); + RADEON_ENC_CS(pps->flags.cu_qp_delta_enabled_flag); } - ENC_END; + RADEON_ENC_END(); } static void @@ -627,19 +623,18 @@ radv_enc_slice_control_hevc(struct radv_cmd_buffer *cmd_buffer, const struct VkV { struct radv_device *device = radv_cmd_buffer_device(cmd_buffer); const struct radv_physical_device *pdev = radv_device_physical(device); - struct radeon_cmdbuf *cs = cmd_buffer->cs; uint32_t width_in_ctb, height_in_ctb, num_ctbs_in_slice; width_in_ctb = DIV_ROUND_UP(enc_info->srcPictureResource.codedExtent.width, 64); height_in_ctb = DIV_ROUND_UP(enc_info->srcPictureResource.codedExtent.height, 64); num_ctbs_in_slice = width_in_ctb * height_in_ctb; - ENC_BEGIN; - radeon_emit(cs, pdev->vcn_enc_cmds.slice_control_hevc); - radeon_emit(cs, RENCODE_HEVC_SLICE_CONTROL_MODE_FIXED_CTBS); - radeon_emit(cs, num_ctbs_in_slice); // num_ctbs_in_slice - radeon_emit(cs, num_ctbs_in_slice); // num_ctbs_in_slice_segment - ENC_END; + + RADEON_ENC_BEGIN(pdev->vcn_enc_cmds.slice_control_hevc); + RADEON_ENC_CS(RENCODE_HEVC_SLICE_CONTROL_MODE_FIXED_CTBS); + RADEON_ENC_CS(num_ctbs_in_slice); // num_ctbs_in_slice + RADEON_ENC_CS(num_ctbs_in_slice); // num_ctbs_in_slice_segment + RADEON_ENC_END(); } static void @@ -647,13 +642,12 @@ radv_enc_rc_session_init(struct radv_cmd_buffer *cmd_buffer) { struct radv_device *device = radv_cmd_buffer_device(cmd_buffer); const struct radv_physical_device *pdev = radv_device_physical(device); - struct radeon_cmdbuf *cs = cmd_buffer->cs; struct radv_video_session *vid = cmd_buffer->video.vid; - ENC_BEGIN; - radeon_emit(cs, pdev->vcn_enc_cmds.rc_session_init); - radeon_emit(cs, vid->enc_rate_control_method); // rate_control_method); - radeon_emit(cs, vid->enc_vbv_buffer_level); // vbv_buffer_level); - ENC_END; + + RADEON_ENC_BEGIN(pdev->vcn_enc_cmds.rc_session_init); + RADEON_ENC_CS(vid->enc_rate_control_method); // rate_control_method); + RADEON_ENC_CS(vid->enc_vbv_buffer_level); // vbv_buffer_level); + RADEON_ENC_END(); } static void @@ -661,18 +655,17 @@ radv_enc_rc_layer_init(struct radv_cmd_buffer *cmd_buffer, rvcn_enc_rate_ctl_lay { struct radv_device *device = radv_cmd_buffer_device(cmd_buffer); const struct radv_physical_device *pdev = radv_device_physical(device); - struct radeon_cmdbuf *cs = cmd_buffer->cs; - ENC_BEGIN; - radeon_emit(cs, pdev->vcn_enc_cmds.rc_layer_init); - radeon_emit(cs, layer_init->target_bit_rate); // target bit rate - radeon_emit(cs, layer_init->peak_bit_rate); // peak bit rate - radeon_emit(cs, layer_init->frame_rate_num); // frame rate num - radeon_emit(cs, layer_init->frame_rate_den); // frame rate dem - radeon_emit(cs, layer_init->vbv_buffer_size); // vbv buffer size - radeon_emit(cs, layer_init->avg_target_bits_per_picture); // avg target bits per picture - radeon_emit(cs, layer_init->peak_bits_per_picture_integer); // peak bit per picture int - radeon_emit(cs, layer_init->peak_bits_per_picture_fractional); // peak bit per picture fract - ENC_END; + + RADEON_ENC_BEGIN(pdev->vcn_enc_cmds.rc_layer_init); + RADEON_ENC_CS(layer_init->target_bit_rate); // target bit rate + RADEON_ENC_CS(layer_init->peak_bit_rate); // peak bit rate + RADEON_ENC_CS(layer_init->frame_rate_num); // frame rate num + RADEON_ENC_CS(layer_init->frame_rate_den); // frame rate dem + RADEON_ENC_CS(layer_init->vbv_buffer_size); // vbv buffer size + RADEON_ENC_CS(layer_init->avg_target_bits_per_picture); // avg target bits per picture + RADEON_ENC_CS(layer_init->peak_bits_per_picture_integer); // peak bit per picture int + RADEON_ENC_CS(layer_init->peak_bits_per_picture_fractional); // peak bit per picture fract + RADEON_ENC_END(); } static void @@ -680,19 +673,18 @@ radv_enc_deblocking_filter_h264(struct radv_cmd_buffer *cmd_buffer, const VkVide { struct radv_device *device = radv_cmd_buffer_device(cmd_buffer); const struct radv_physical_device *pdev = radv_device_physical(device); - struct radeon_cmdbuf *cs = cmd_buffer->cs; const struct VkVideoEncodeH264PictureInfoKHR *h264_picture_info = vk_find_struct_const(enc_info->pNext, VIDEO_ENCODE_H264_PICTURE_INFO_KHR); const VkVideoEncodeH264NaluSliceInfoKHR *h264_slice = &h264_picture_info->pNaluSliceEntries[0]; const StdVideoEncodeH264SliceHeader *slice = h264_slice->pStdSliceHeader; - ENC_BEGIN; - radeon_emit(cs, pdev->vcn_enc_cmds.deblocking_filter_h264); - radeon_emit(cs, slice->disable_deblocking_filter_idc); - radeon_emit(cs, slice->slice_alpha_c0_offset_div2); - radeon_emit(cs, slice->slice_beta_offset_div2); - radeon_emit(cs, 0); // cb qp offset - radeon_emit(cs, 0); // cr qp offset - ENC_END; + + RADEON_ENC_BEGIN(pdev->vcn_enc_cmds.deblocking_filter_h264); + RADEON_ENC_CS(slice->disable_deblocking_filter_idc); + RADEON_ENC_CS(slice->slice_alpha_c0_offset_div2); + RADEON_ENC_CS(slice->slice_beta_offset_div2); + RADEON_ENC_CS(0); // cb qp offset + RADEON_ENC_CS(0); // cr qp offset + RADEON_ENC_END(); } static void @@ -700,7 +692,6 @@ radv_enc_deblocking_filter_hevc(struct radv_cmd_buffer *cmd_buffer, const VkVide { struct radv_device *device = radv_cmd_buffer_device(cmd_buffer); const struct radv_physical_device *pdev = radv_device_physical(device); - struct radeon_cmdbuf *cs = cmd_buffer->cs; const struct VkVideoEncodeH265PictureInfoKHR *h265_picture_info = vk_find_struct_const(enc_info->pNext, VIDEO_ENCODE_H265_PICTURE_INFO_KHR); const StdVideoEncodeH265PictureInfo *pic = h265_picture_info->pStdPictureInfo; @@ -709,17 +700,16 @@ radv_enc_deblocking_filter_hevc(struct radv_cmd_buffer *cmd_buffer, const VkVide const StdVideoH265SequenceParameterSet *sps = vk_video_find_h265_enc_std_sps(&cmd_buffer->video.params->vk, pic->pps_seq_parameter_set_id); - ENC_BEGIN; - radeon_emit(cs, pdev->vcn_enc_cmds.deblocking_filter_hevc); - radeon_emit(cs, slice->flags.slice_loop_filter_across_slices_enabled_flag); - radeon_emit(cs, slice->flags.slice_deblocking_filter_disabled_flag); - radeon_emit(cs, slice->slice_beta_offset_div2); - radeon_emit(cs, slice->slice_tc_offset_div2); - radeon_emit(cs, slice->slice_cb_qp_offset); - radeon_emit(cs, slice->slice_cr_qp_offset); + RADEON_ENC_BEGIN(pdev->vcn_enc_cmds.deblocking_filter_hevc); + RADEON_ENC_CS(slice->flags.slice_loop_filter_across_slices_enabled_flag); + RADEON_ENC_CS(slice->flags.slice_deblocking_filter_disabled_flag); + RADEON_ENC_CS(slice->slice_beta_offset_div2); + RADEON_ENC_CS(slice->slice_tc_offset_div2); + RADEON_ENC_CS(slice->slice_cb_qp_offset); + RADEON_ENC_CS(slice->slice_cr_qp_offset); if (pdev->enc_hw_ver >= RADV_VIDEO_ENC_HW_2) - radeon_emit(cs, !sps->flags.sample_adaptive_offset_enabled_flag); - ENC_END; + RADEON_ENC_CS(!sps->flags.sample_adaptive_offset_enabled_flag); + RADEON_ENC_END(); } static void @@ -727,16 +717,15 @@ radv_enc_quality_params(struct radv_cmd_buffer *cmd_buffer) { struct radv_device *device = radv_cmd_buffer_device(cmd_buffer); const struct radv_physical_device *pdev = radv_device_physical(device); - struct radeon_cmdbuf *cs = cmd_buffer->cs; - ENC_BEGIN; - radeon_emit(cs, pdev->vcn_enc_cmds.quality_params); - radeon_emit(cs, 0); - radeon_emit(cs, 0); - radeon_emit(cs, 0); - radeon_emit(cs, 0); + + RADEON_ENC_BEGIN(pdev->vcn_enc_cmds.quality_params); + RADEON_ENC_CS(0); + RADEON_ENC_CS(0); + RADEON_ENC_CS(0); + RADEON_ENC_CS(0); if (pdev->enc_hw_ver >= RADV_VIDEO_ENC_HW_2) - radeon_emit(cs, 0); - ENC_END; + RADEON_ENC_CS(0); + RADEON_ENC_END(); } static void @@ -744,14 +733,12 @@ radv_enc_latency(struct radv_cmd_buffer *cmd_buffer, VkVideoEncodeTuningModeKHR { struct radv_device *device = radv_cmd_buffer_device(cmd_buffer); const struct radv_physical_device *pdev = radv_device_physical(device); - struct radeon_cmdbuf *cs = cmd_buffer->cs; if (tuning_mode == VK_VIDEO_ENCODE_TUNING_MODE_LOW_LATENCY_KHR || tuning_mode == VK_VIDEO_ENCODE_TUNING_MODE_ULTRA_LOW_LATENCY_KHR) { - ENC_BEGIN; - radeon_emit(cs, pdev->vcn_enc_cmds.enc_latency); - radeon_emit(cs, 1000); - ENC_END; + RADEON_ENC_BEGIN(pdev->vcn_enc_cmds.enc_latency); + RADEON_ENC_CS(1000); + RADEON_ENC_END(); } } @@ -781,8 +768,8 @@ radv_enc_slice_header(struct radv_cmd_buffer *cmd_buffer, const VkVideoEncodeInf struct radv_device *device = radv_cmd_buffer_device(cmd_buffer); const struct radv_physical_device *pdev = radv_device_physical(device); struct radeon_cmdbuf *cs = cmd_buffer->cs; - ENC_BEGIN; - radeon_emit(cs, pdev->vcn_enc_cmds.slice_header); + + RADEON_ENC_BEGIN(pdev->vcn_enc_cmds.slice_header); radv_enc_reset(cmd_buffer); radv_enc_set_emulation_prevention(cmd_buffer, false); @@ -948,12 +935,12 @@ radv_enc_slice_header(struct radv_cmd_buffer *cmd_buffer, const VkVideoEncodeInf cdw_filled = cs->cdw - cdw_start; for (int i = 0; i < RENCODE_SLICE_HEADER_TEMPLATE_MAX_TEMPLATE_SIZE_IN_DWORDS - cdw_filled; i++) - radeon_emit(cs, 0x00000000); + RADEON_ENC_CS(0x00000000); for (int j = 0; j < RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS; j++) { - radeon_emit(cs, instruction[j]); - radeon_emit(cs, num_bits[j]); + RADEON_ENC_CS(instruction[j]); + RADEON_ENC_CS(num_bits[j]); } - ENC_END; + RADEON_ENC_END(); } static void @@ -980,8 +967,7 @@ radv_enc_slice_header_hevc(struct radv_cmd_buffer *cmd_buffer, const VkVideoEnco struct radeon_cmdbuf *cs = cmd_buffer->cs; unsigned nal_unit_type = vk_video_get_h265_nal_unit(pic); - ENC_BEGIN; - radeon_emit(cs, pdev->vcn_enc_cmds.slice_header); + RADEON_ENC_BEGIN(pdev->vcn_enc_cmds.slice_header); radv_enc_reset(cmd_buffer); radv_enc_set_emulation_prevention(cmd_buffer, false); @@ -1164,12 +1150,12 @@ radv_enc_slice_header_hevc(struct radv_cmd_buffer *cmd_buffer, const VkVideoEnco cdw_filled = cs->cdw - cdw_start; for (int i = 0; i < RENCODE_SLICE_HEADER_TEMPLATE_MAX_TEMPLATE_SIZE_IN_DWORDS - cdw_filled; i++) - radeon_emit(cs, 0x00000000); + RADEON_ENC_CS(0x00000000); for (int j = 0; j < RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS; j++) { - radeon_emit(cs, instruction[j]); - radeon_emit(cs, num_bits[j]); + RADEON_ENC_CS(instruction[j]); + RADEON_ENC_CS(num_bits[j]); } - ENC_END; + RADEON_ENC_END(); } static void @@ -1240,14 +1226,14 @@ radv_enc_ctx(struct radv_cmd_buffer *cmd_buffer, const VkVideoEncodeInfoKHR *inf swizzle_mode = RENCODE_REC_SWIZZLE_MODE_256B_D; else if (pdev->enc_hw_ver >= RADV_VIDEO_ENC_HW_2) swizzle_mode = RENCODE_REC_SWIZZLE_MODE_256B_S; - ENC_BEGIN; - radeon_emit(cs, pdev->vcn_enc_cmds.ctx); - radeon_emit(cs, va >> 32); - radeon_emit(cs, va & 0xffffffff); - radeon_emit(cs, swizzle_mode); - radeon_emit(cs, luma_pitch); // rec_luma_pitch - radeon_emit(cs, luma_pitch); // rec_luma_pitch0); //rec_chromma_pitch - radeon_emit(cs, max_ref_slot_idx + 1); // num_reconstructed_pictures + + RADEON_ENC_BEGIN(pdev->vcn_enc_cmds.ctx); + RADEON_ENC_CS(va >> 32); + RADEON_ENC_CS(va & 0xffffffff); + RADEON_ENC_CS(swizzle_mode); + RADEON_ENC_CS(luma_pitch); // rec_luma_pitch + RADEON_ENC_CS(luma_pitch); // rec_luma_pitch0); //rec_chromma_pitch + RADEON_ENC_CS(max_ref_slot_idx + 1); // num_reconstructed_pictures int i; unsigned offset = 0; @@ -1259,66 +1245,66 @@ radv_enc_ctx(struct radv_cmd_buffer *cmd_buffer, const VkVideoEncodeInfoKHR *inf offset += colloc_bytes; } for (i = 0; i < max_ref_slot_idx + 1; i++) { - radeon_emit(cs, offset); + RADEON_ENC_CS(offset); offset += luma_size; - radeon_emit(cs, offset); + RADEON_ENC_CS(offset); offset += chroma_size; if (pdev->enc_hw_ver >= RADV_VIDEO_ENC_HW_4) { - radeon_emit(cs, 0); /* unused offset 1 */ - radeon_emit(cs, 0); /* unused offset 2 */ + RADEON_ENC_CS(0); /* unused offset 1 */ + RADEON_ENC_CS(0); /* unused offset 2 */ } } for (; i < RENCODE_MAX_NUM_RECONSTRUCTED_PICTURES; i++) { - radeon_emit(cs, 0); - radeon_emit(cs, 0); + RADEON_ENC_CS(0); + RADEON_ENC_CS(0); if (pdev->enc_hw_ver >= RADV_VIDEO_ENC_HW_4) { - radeon_emit(cs, 0); /* unused offset 1 */ - radeon_emit(cs, 0); /* unused offset 2 */ + RADEON_ENC_CS(0); /* unused offset 1 */ + RADEON_ENC_CS(0); /* unused offset 2 */ } } if (pdev->enc_hw_ver == RADV_VIDEO_ENC_HW_3) { - radeon_emit(cs, colloc_buffer_offset); + RADEON_ENC_CS(colloc_buffer_offset); } - radeon_emit(cs, 0); // enc pic pre encode luma pitch - radeon_emit(cs, 0); // enc pic pre encode chroma pitch + RADEON_ENC_CS(0); // enc pic pre encode luma pitch + RADEON_ENC_CS(0); // enc pic pre encode chroma pitch for (i = 0; i < RENCODE_MAX_NUM_RECONSTRUCTED_PICTURES; i++) { - radeon_emit(cs, 0); // pre encode luma offset - radeon_emit(cs, 0); // pre encode chroma offset + RADEON_ENC_CS(0); // pre encode luma offset + RADEON_ENC_CS(0); // pre encode chroma offset if (pdev->enc_hw_ver >= RADV_VIDEO_ENC_HW_4) { - radeon_emit(cs, 0); /* unused offset 1 */ - radeon_emit(cs, 0); /* unused offset 2 */ + RADEON_ENC_CS(0); /* unused offset 1 */ + RADEON_ENC_CS(0); /* unused offset 2 */ } } if (pdev->enc_hw_ver == RADV_VIDEO_ENC_HW_2) { - radeon_emit(cs, 0); // enc pic yuv luma offset - radeon_emit(cs, 0); // enc pic yuv chroma offset + RADEON_ENC_CS(0); // enc pic yuv luma offset + RADEON_ENC_CS(0); // enc pic yuv chroma offset - radeon_emit(cs, 0); // two pass search center map offset + RADEON_ENC_CS(0); // two pass search center map offset // rgboffsets - radeon_emit(cs, 0); // red - radeon_emit(cs, 0); // green - radeon_emit(cs, 0); // blue + RADEON_ENC_CS(0); // red + RADEON_ENC_CS(0); // green + RADEON_ENC_CS(0); // blue } else if (pdev->enc_hw_ver >= RADV_VIDEO_ENC_HW_3) { - radeon_emit(cs, 0); // red - radeon_emit(cs, 0); // green - radeon_emit(cs, 0); // blue - radeon_emit(cs, 0); // v3 two pass search center map offset + RADEON_ENC_CS(0); // red + RADEON_ENC_CS(0); // green + RADEON_ENC_CS(0); // blue + RADEON_ENC_CS(0); // v3 two pass search center map offset if (pdev->enc_hw_ver >= RADV_VIDEO_ENC_HW_4) { - radeon_emit(cs, colloc_buffer_offset); + RADEON_ENC_CS(colloc_buffer_offset); } else { - radeon_emit(cs, 0); + RADEON_ENC_CS(0); } if (pdev->enc_hw_ver == RADV_VIDEO_ENC_HW_3) { - radeon_emit(cs, 0); + RADEON_ENC_CS(0); } } - ENC_END; + RADEON_ENC_END(); } static void @@ -1330,14 +1316,13 @@ radv_enc_bitstream(struct radv_cmd_buffer *cmd_buffer, struct radv_buffer *buffe uint64_t va = vk_buffer_address(&buffer->vk, offset); radv_cs_add_buffer(device->ws, cs, buffer->bo); - ENC_BEGIN; - radeon_emit(cs, pdev->vcn_enc_cmds.bitstream); - radeon_emit(cs, RENCODE_REC_SWIZZLE_MODE_LINEAR); - radeon_emit(cs, va >> 32); - radeon_emit(cs, va & 0xffffffff); - radeon_emit(cs, buffer->vk.size); - radeon_emit(cs, 0); - ENC_END; + RADEON_ENC_BEGIN(pdev->vcn_enc_cmds.bitstream); + RADEON_ENC_CS(RENCODE_REC_SWIZZLE_MODE_LINEAR); + RADEON_ENC_CS(va >> 32); + RADEON_ENC_CS(va & 0xffffffff); + RADEON_ENC_CS(buffer->vk.size); + RADEON_ENC_CS(0); + RADEON_ENC_END(); } static void @@ -1345,16 +1330,14 @@ radv_enc_feedback(struct radv_cmd_buffer *cmd_buffer, uint64_t feedback_query_va { struct radv_device *device = radv_cmd_buffer_device(cmd_buffer); const struct radv_physical_device *pdev = radv_device_physical(device); - struct radeon_cmdbuf *cs = cmd_buffer->cs; - ENC_BEGIN; - radeon_emit(cs, pdev->vcn_enc_cmds.feedback); - radeon_emit(cs, RENCODE_FEEDBACK_BUFFER_MODE_LINEAR); - radeon_emit(cs, feedback_query_va >> 32); - radeon_emit(cs, feedback_query_va & 0xffffffff); - radeon_emit(cs, 16); // buffer_size - radeon_emit(cs, 40); // data_size - ENC_END; + RADEON_ENC_BEGIN(pdev->vcn_enc_cmds.feedback); + RADEON_ENC_CS(RENCODE_FEEDBACK_BUFFER_MODE_LINEAR); + RADEON_ENC_CS(feedback_query_va >> 32); + RADEON_ENC_CS(feedback_query_va & 0xffffffff); + RADEON_ENC_CS(16); // buffer_size + RADEON_ENC_CS(40); // data_size + RADEON_ENC_END(); } static void @@ -1362,13 +1345,12 @@ radv_enc_intra_refresh(struct radv_cmd_buffer *cmd_buffer) { struct radv_device *device = radv_cmd_buffer_device(cmd_buffer); const struct radv_physical_device *pdev = radv_device_physical(device); - struct radeon_cmdbuf *cs = cmd_buffer->cs; - ENC_BEGIN; - radeon_emit(cs, pdev->vcn_enc_cmds.intra_refresh); - radeon_emit(cs, 0); // intra refresh mode - radeon_emit(cs, 0); // intra ref offset - radeon_emit(cs, 0); // intra region size - ENC_END; + + RADEON_ENC_BEGIN(pdev->vcn_enc_cmds.intra_refresh); + RADEON_ENC_CS(0); // intra refresh mode + RADEON_ENC_CS(0); // intra ref offset + RADEON_ENC_CS(0); // intra region size + RADEON_ENC_END(); } static void @@ -1378,7 +1360,6 @@ radv_enc_rc_per_pic(struct radv_cmd_buffer *cmd_buffer, const VkVideoEncodeInfoK struct radv_video_session *vid = cmd_buffer->video.vid; struct radv_device *device = radv_cmd_buffer_device(cmd_buffer); const struct radv_physical_device *pdev = radv_device_physical(device); - struct radeon_cmdbuf *cs = cmd_buffer->cs; unsigned qp = per_pic->qp_i; @@ -1402,25 +1383,25 @@ radv_enc_rc_per_pic(struct radv_cmd_buffer *cmd_buffer, const VkVideoEncodeInfoK break; } } - ENC_BEGIN; - radeon_emit(cs, pdev->vcn_enc_cmds.rc_per_pic); - radeon_emit(cs, qp); // qp_i - radeon_emit(cs, qp); // qp_p - radeon_emit(cs, qp); // qp_b - radeon_emit(cs, per_pic->min_qp_i); - radeon_emit(cs, per_pic->max_qp_i); - radeon_emit(cs, per_pic->min_qp_p); - radeon_emit(cs, per_pic->max_qp_p); - radeon_emit(cs, per_pic->min_qp_b); - radeon_emit(cs, per_pic->max_qp_b); - radeon_emit(cs, per_pic->max_au_size_i); - radeon_emit(cs, per_pic->max_au_size_p); - radeon_emit(cs, per_pic->max_au_size_b); - radeon_emit(cs, per_pic->enabled_filler_data); - radeon_emit(cs, per_pic->skip_frame_enable); - radeon_emit(cs, per_pic->enforce_hrd); - radeon_emit(cs, 0xFFFFFFFF); // reserved_0xff - ENC_END; + + RADEON_ENC_BEGIN(pdev->vcn_enc_cmds.rc_per_pic); + RADEON_ENC_CS(qp); // qp_i + RADEON_ENC_CS(qp); // qp_p + RADEON_ENC_CS(qp); // qp_b + RADEON_ENC_CS(per_pic->min_qp_i); + RADEON_ENC_CS(per_pic->max_qp_i); + RADEON_ENC_CS(per_pic->min_qp_p); + RADEON_ENC_CS(per_pic->max_qp_p); + RADEON_ENC_CS(per_pic->min_qp_b); + RADEON_ENC_CS(per_pic->max_qp_b); + RADEON_ENC_CS(per_pic->max_au_size_i); + RADEON_ENC_CS(per_pic->max_au_size_p); + RADEON_ENC_CS(per_pic->max_au_size_b); + RADEON_ENC_CS(per_pic->enabled_filler_data); + RADEON_ENC_CS(per_pic->skip_frame_enable); + RADEON_ENC_CS(per_pic->enforce_hrd); + RADEON_ENC_CS(0xFFFFFFFF); // reserved_0xff + RADEON_ENC_END(); } static void @@ -1484,24 +1465,23 @@ radv_enc_params(struct radv_cmd_buffer *cmd_buffer, const VkVideoEncodeInfoKHR * return; } - ENC_BEGIN; - radeon_emit(cs, pdev->vcn_enc_cmds.enc_params); - radeon_emit(cs, pic_type); // pic type - radeon_emit(cs, enc_info->dstBufferRange); // allowed max bitstream size - radeon_emit(cs, luma_va >> 32); - radeon_emit(cs, luma_va & 0xffffffff); - radeon_emit(cs, chroma_va >> 32); - radeon_emit(cs, chroma_va & 0xffffffff); - radeon_emit(cs, src_img->planes[0].surface.u.gfx9.surf_pitch); // luma pitch - radeon_emit(cs, src_img->planes[1].surface.u.gfx9.surf_pitch); // chroma pitch - radeon_emit(cs, src_img->planes[0].surface.u.gfx9.swizzle_mode); // swizzle mode - radeon_emit(cs, slot_idx); // ref0_idx + RADEON_ENC_BEGIN(pdev->vcn_enc_cmds.enc_params); + RADEON_ENC_CS(pic_type); // pic type + RADEON_ENC_CS(enc_info->dstBufferRange); // allowed max bitstream size + RADEON_ENC_CS(luma_va >> 32); + RADEON_ENC_CS(luma_va & 0xffffffff); + RADEON_ENC_CS(chroma_va >> 32); + RADEON_ENC_CS(chroma_va & 0xffffffff); + RADEON_ENC_CS(src_img->planes[0].surface.u.gfx9.surf_pitch); // luma pitch + RADEON_ENC_CS(src_img->planes[1].surface.u.gfx9.surf_pitch); // chroma pitch + RADEON_ENC_CS(src_img->planes[0].surface.u.gfx9.swizzle_mode); // swizzle mode + RADEON_ENC_CS(slot_idx); // ref0_idx if (enc_info->pSetupReferenceSlot) - radeon_emit(cs, enc_info->pSetupReferenceSlot->slotIndex); // reconstructed picture index + RADEON_ENC_CS(enc_info->pSetupReferenceSlot->slotIndex); // reconstructed picture index else - radeon_emit(cs, 0); - ENC_END; + RADEON_ENC_CS(0); + RADEON_ENC_END(); } static void @@ -1510,7 +1490,6 @@ radv_enc_params_h264(struct radv_cmd_buffer *cmd_buffer, { struct radv_device *device = radv_cmd_buffer_device(cmd_buffer); const struct radv_physical_device *pdev = radv_device_physical(device); - struct radeon_cmdbuf *cs = cmd_buffer->cs; const struct VkVideoEncodeH264PictureInfoKHR *h264_picture_info = vk_find_struct_const(enc_info->pNext, VIDEO_ENCODE_H264_PICTURE_INFO_KHR); @@ -1526,78 +1505,69 @@ radv_enc_params_h264(struct radv_cmd_buffer *cmd_buffer, default: break; } - ENC_BEGIN; - radeon_emit(cs, pdev->vcn_enc_cmds.enc_params_h264); + + RADEON_ENC_BEGIN(pdev->vcn_enc_cmds.enc_params_h264); if (pdev->enc_hw_ver < RADV_VIDEO_ENC_HW_3) { - radeon_emit(cs, RENCODE_H264_PICTURE_STRUCTURE_FRAME); - radeon_emit(cs, RENCODE_H264_INTERLACING_MODE_PROGRESSIVE); - radeon_emit(cs, RENCODE_H264_PICTURE_STRUCTURE_FRAME); - radeon_emit(cs, 0xffffffff); // reference_picture1_index + RADEON_ENC_CS(RENCODE_H264_PICTURE_STRUCTURE_FRAME); + RADEON_ENC_CS(RENCODE_H264_INTERLACING_MODE_PROGRESSIVE); + RADEON_ENC_CS(RENCODE_H264_PICTURE_STRUCTURE_FRAME); + RADEON_ENC_CS(0xffffffff); // reference_picture1_index } else { // V3 - radeon_emit(cs, RENCODE_H264_PICTURE_STRUCTURE_FRAME); - radeon_emit(cs, 0); // input pic order cnt - radeon_emit(cs, RENCODE_H264_INTERLACING_MODE_PROGRESSIVE); - radeon_emit(cs, 0); // l0 ref pic0 pic_type - radeon_emit(cs, 0); // l0 ref pic0 is long term - radeon_emit(cs, 0); // l0 ref pic0 picture structure - radeon_emit(cs, 0); // l0 ref pic0 pic order cnt - radeon_emit(cs, 0xffffffff); // l0 ref pic1 index - radeon_emit(cs, 0); // l0 ref pic1 pic_type - radeon_emit(cs, 0); // l0 ref pic1 is long term - radeon_emit(cs, 0); // l0 ref pic1 picture structure - radeon_emit(cs, 0); // l0 ref pic1 pic order cnt - radeon_emit(cs, slot_idx_1); // l1 ref pic0 index - radeon_emit(cs, 0); // l1 ref pic0 pic_type - radeon_emit(cs, 0); // l1 ref pic0 is long term - radeon_emit(cs, 0); // l1 ref pic0 picture structure - radeon_emit(cs, 0); // l1 ref pic0 pic order cnt - radeon_emit(cs, h264_pic->flags.is_reference); // is reference + RADEON_ENC_CS(RENCODE_H264_PICTURE_STRUCTURE_FRAME); + RADEON_ENC_CS(0); // input pic order cnt + RADEON_ENC_CS(RENCODE_H264_INTERLACING_MODE_PROGRESSIVE); + RADEON_ENC_CS(0); // l0 ref pic0 pic_type + RADEON_ENC_CS(0); // l0 ref pic0 is long term + RADEON_ENC_CS(0); // l0 ref pic0 picture structure + RADEON_ENC_CS(0); // l0 ref pic0 pic order cnt + RADEON_ENC_CS(0xffffffff); // l0 ref pic1 index + RADEON_ENC_CS(0); // l0 ref pic1 pic_type + RADEON_ENC_CS(0); // l0 ref pic1 is long term + RADEON_ENC_CS(0); // l0 ref pic1 picture structure + RADEON_ENC_CS(0); // l0 ref pic1 pic order cnt + RADEON_ENC_CS(slot_idx_1); // l1 ref pic0 index + RADEON_ENC_CS(0); // l1 ref pic0 pic_type + RADEON_ENC_CS(0); // l1 ref pic0 is long term + RADEON_ENC_CS(0); // l1 ref pic0 picture structure + RADEON_ENC_CS(0); // l1 ref pic0 pic order cnt + RADEON_ENC_CS(h264_pic->flags.is_reference); // is reference } - ENC_END; + RADEON_ENC_END(); } static void radv_enc_op_init(struct radv_cmd_buffer *cmd_buffer) { - struct radeon_cmdbuf *cs = cmd_buffer->cs; - ENC_BEGIN; - radeon_emit(cs, RENCODE_IB_OP_INITIALIZE); - ENC_END; + RADEON_ENC_BEGIN(RENCODE_IB_OP_INITIALIZE); + RADEON_ENC_END(); } static void radv_enc_op_enc(struct radv_cmd_buffer *cmd_buffer) { - struct radeon_cmdbuf *cs = cmd_buffer->cs; - ENC_BEGIN; - radeon_emit(cs, RENCODE_IB_OP_ENCODE); - ENC_END; + RADEON_ENC_BEGIN(RENCODE_IB_OP_ENCODE); + RADEON_ENC_END(); } static void radv_enc_op_init_rc(struct radv_cmd_buffer *cmd_buffer) { - struct radeon_cmdbuf *cs = cmd_buffer->cs; - ENC_BEGIN; - radeon_emit(cs, RENCODE_IB_OP_INIT_RC); - ENC_END; + RADEON_ENC_BEGIN(RENCODE_IB_OP_INIT_RC); + RADEON_ENC_END(); } static void radv_enc_op_init_rc_vbv(struct radv_cmd_buffer *cmd_buffer) { - struct radeon_cmdbuf *cs = cmd_buffer->cs; - ENC_BEGIN; - radeon_emit(cs, RENCODE_IB_OP_INIT_RC_VBV_BUFFER_LEVEL); - ENC_END; + RADEON_ENC_BEGIN(RENCODE_IB_OP_INIT_RC_VBV_BUFFER_LEVEL); + RADEON_ENC_END(); } static void radv_enc_op_preset(struct radv_cmd_buffer *cmd_buffer, const VkVideoEncodeInfoKHR *enc_info) { - struct radeon_cmdbuf *cs = cmd_buffer->cs; struct radv_video_session *vid = cmd_buffer->video.vid; uint32_t preset_mode; @@ -1623,9 +1593,8 @@ radv_enc_op_preset(struct radv_cmd_buffer *cmd_buffer, const VkVideoEncodeInfoKH break; } - ENC_BEGIN; - radeon_emit(cs, preset_mode); - ENC_END; + RADEON_ENC_BEGIN(preset_mode); + RADEON_ENC_END(); } static void @@ -1633,7 +1602,6 @@ radv_enc_input_format(struct radv_cmd_buffer *cmd_buffer) { struct radv_device *device = radv_cmd_buffer_device(cmd_buffer); const struct radv_physical_device *pdev = radv_device_physical(device); - struct radeon_cmdbuf *cs = cmd_buffer->cs; struct radv_video_session *vid = cmd_buffer->video.vid; uint32_t color_bit_depth; uint32_t color_packing_format; @@ -1652,16 +1620,15 @@ radv_enc_input_format(struct radv_cmd_buffer *cmd_buffer) return; } - ENC_BEGIN; - radeon_emit(cs, pdev->vcn_enc_cmds.input_format); - radeon_emit(cs, 0); // input color volume - radeon_emit(cs, 0); // input color space - radeon_emit(cs, RENCODE_COLOR_RANGE_STUDIO); // input color range - radeon_emit(cs, 0); // input chroma subsampling - radeon_emit(cs, 0); // input chroma location - radeon_emit(cs, color_bit_depth); // input color bit depth - radeon_emit(cs, color_packing_format); // input color packing format - ENC_END; + RADEON_ENC_BEGIN(pdev->vcn_enc_cmds.input_format); + RADEON_ENC_CS(0); // input color volume + RADEON_ENC_CS(0); // input color space + RADEON_ENC_CS(RENCODE_COLOR_RANGE_STUDIO); // input color range + RADEON_ENC_CS(0); // input chroma subsampling + RADEON_ENC_CS(0); // input chroma location + RADEON_ENC_CS(color_bit_depth); // input color bit depth + RADEON_ENC_CS(color_packing_format); // input color packing format + RADEON_ENC_END(); } static void @@ -1669,7 +1636,6 @@ radv_enc_output_format(struct radv_cmd_buffer *cmd_buffer) { struct radv_device *device = radv_cmd_buffer_device(cmd_buffer); const struct radv_physical_device *pdev = radv_device_physical(device); - struct radeon_cmdbuf *cs = cmd_buffer->cs; struct radv_video_session *vid = cmd_buffer->video.vid; uint32_t color_bit_depth; @@ -1688,13 +1654,12 @@ radv_enc_output_format(struct radv_cmd_buffer *cmd_buffer) return; } - ENC_BEGIN; - radeon_emit(cs, pdev->vcn_enc_cmds.output_format); - radeon_emit(cs, 0); // output color volume - radeon_emit(cs, RENCODE_COLOR_RANGE_STUDIO); // output color range - radeon_emit(cs, 0); // output chroma location - radeon_emit(cs, color_bit_depth); // output color bit depth - ENC_END; + RADEON_ENC_BEGIN(pdev->vcn_enc_cmds.output_format); + RADEON_ENC_CS(0); // output color volume + RADEON_ENC_CS(RENCODE_COLOR_RANGE_STUDIO); // output color range + RADEON_ENC_CS(0); // output chroma location + RADEON_ENC_CS(color_bit_depth); // output color bit depth + RADEON_ENC_END(); } static void