From bfd56a1fdd05635425e0f3a403a1d3367d1eefc7 Mon Sep 17 00:00:00 2001
From: Danylo Piliaiev <dpiliaiev@igalia.com>
Date: Fri, 15 Mar 2024 15:37:11 +0100
Subject: [PATCH] freedreno,tu/a7xx: Add PC_TESS_PARAM_SIZE and
 PC_TESS_FACTOR_SIZE

A750 adds explicit definition of PC_TESS_PARAM_SIZE and
PC_TESS_FACTOR_SIZE, probably in order to to correctly overlap execution
of several draws.

Note that blob adds a bit more space ({0x10, 0x20, 0x30, 0x40} bytes)
to PC_TESS_FACTOR_SIZE than we are, but the purpose of this additional
space is unknown.

Emitting these regs on whole A7XX seem to be fine - A740 doesn't
complain.

Fixes GPU faults in Witcher 3.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28210>
---
 src/freedreno/registers/adreno/a6xx.xml |  9 +++++++++
 src/freedreno/vulkan/tu_cmd_buffer.cc   | 10 ++++++++++
 2 files changed, 19 insertions(+)

diff --git a/src/freedreno/registers/adreno/a6xx.xml b/src/freedreno/registers/adreno/a6xx.xml
index 78524aaab9d..0a2fecca4d1 100644
--- a/src/freedreno/registers/adreno/a6xx.xml
+++ b/src/freedreno/registers/adreno/a6xx.xml
@@ -3306,6 +3306,15 @@ to upconvert to 32b float internally?
 		<bitfield name="DISCARD" pos="2" type="boolean"/>
 	</reg32>
 
+	<!-- Both are a750+.
+	     Probably needed to correctly overlap execution of several draws.
+	-->
+	<reg32 offset="0x9885" name="PC_TESS_PARAM_SIZE" variants="A7XX-" usage="cmd"/>
+	<!-- Blob adds a bit more space {0x10, 0x20, 0x30, 0x40} bytes, but the meaning of
+	     this additional space is not known.
+	-->
+	<reg32 offset="0x9886" name="PC_TESS_FACTOR_SIZE" variants="A7XX-" usage="cmd"/>
+
 	<!-- 0x9982-0x9aff invalid -->
 
 	<reg32 offset="0x9b00" name="PC_PRIMITIVE_CNTL_0" type="a6xx_primitive_cntl_0" usage="rp_blit"/>
diff --git a/src/freedreno/vulkan/tu_cmd_buffer.cc b/src/freedreno/vulkan/tu_cmd_buffer.cc
index a32ac8166ac..f754be3c009 100644
--- a/src/freedreno/vulkan/tu_cmd_buffer.cc
+++ b/src/freedreno/vulkan/tu_cmd_buffer.cc
@@ -1373,6 +1373,16 @@ tu6_init_hw(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
       tu_cs_emit_ib(cs, dev->cmdbuf_start_a725_quirk_entry);
    }
 
+   if (CHIP >= A7XX) {
+      /* Blob sets these two per draw. */
+      tu_cs_emit_regs(cs, A7XX_PC_TESS_PARAM_SIZE(TU_TESS_PARAM_SIZE));
+      /* Blob adds a bit more space ({0x10, 0x20, 0x30, 0x40} bytes)
+       * but the meaning of this additional space is not known,
+       * so we play safe and don't add it.
+       */
+      tu_cs_emit_regs(cs, A7XX_PC_TESS_FACTOR_SIZE(TU_TESS_FACTOR_SIZE));
+   }
+
    tu_cs_sanity_check(cs);
 }