From bfb6d09e95d69ecf94d5f0aff56e3ffa40836c72 Mon Sep 17 00:00:00 2001
From: Connor Abbott <cwabbott0@gmail.com>
Date: Thu, 23 Jan 2025 11:57:54 -0500
Subject: [PATCH] freedreno: Add bin scaling registers

These let us avoid manually patching the viewport as we had to do on
a6xx. However they do not affect blits, so we still have to manually
scale there. They exist from a740.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36475>
---
 src/freedreno/common/freedreno_devices.py | 48 ++++++++++-----------
 src/freedreno/registers/adreno/a6xx.xml   | 51 +++++++++++++++++++----
 2 files changed, 68 insertions(+), 31 deletions(-)

diff --git a/src/freedreno/common/freedreno_devices.py b/src/freedreno/common/freedreno_devices.py
index 8fc040c1e43..5dd267feab2 100644
--- a/src/freedreno/common/freedreno_devices.py
+++ b/src/freedreno/common/freedreno_devices.py
@@ -1025,7 +1025,7 @@ a730_raw_magic_regs = [
 
         [A6XXRegs.REG_A7XX_RB_UNKNOWN_8E79,   0x00000000],
         [A6XXRegs.REG_A7XX_RB_UNKNOWN_8899,   0x00000000],
-        [A6XXRegs.REG_A7XX_RB_UNKNOWN_88F5,   0x00000000],
+        [A6XXRegs.REG_A7XX_RB_BIN_FOVEAT,      0x00000000],
     ]
 
 a740_magic_regs = dict(
@@ -1073,10 +1073,10 @@ a740_raw_magic_regs = [
         [A6XXRegs.REG_A7XX_GRAS_UNKNOWN_8120, 0x09510840],
         [A6XXRegs.REG_A7XX_GRAS_UNKNOWN_8121, 0x00000a62],
 
-        [A6XXRegs.REG_A7XX_GRAS_UNKNOWN_8009, 0x00000000],
-        [A6XXRegs.REG_A7XX_GRAS_UNKNOWN_800A, 0x00000000],
-        [A6XXRegs.REG_A7XX_GRAS_UNKNOWN_800B, 0x00000000],
-        [A6XXRegs.REG_A7XX_GRAS_UNKNOWN_800C, 0x00000000],
+        [A6XXRegs.REG_A7XX_GRAS_BIN_FOVEAT_OFFSET_0, 0x00000000],
+        [A6XXRegs.REG_A7XX_GRAS_BIN_FOVEAT_OFFSET_1, 0x00000000],
+        [A6XXRegs.REG_A7XX_GRAS_BIN_FOVEAT_OFFSET_2, 0x00000000],
+        [A6XXRegs.REG_A7XX_GRAS_BIN_FOVEAT_OFFSET_3, 0x00000000],
 
         [A6XXRegs.REG_A7XX_SP_UNKNOWN_0CE2,   0x00000000],
         [A6XXRegs.REG_A7XX_SP_UNKNOWN_0CE2+1, 0x00000000],
@@ -1089,10 +1089,10 @@ a740_raw_magic_regs = [
 
         [A6XXRegs.REG_A7XX_RB_UNKNOWN_8E79,   0x00000000],
         [A6XXRegs.REG_A7XX_RB_UNKNOWN_8899,   0x00000000],
-        [A6XXRegs.REG_A7XX_RB_UNKNOWN_88F5,   0x00000000],
+        [A6XXRegs.REG_A7XX_RB_BIN_FOVEAT,      0x00000000],
         [A6XXRegs.REG_A7XX_RB_UNKNOWN_8C34,   0x00000000],
 
-        [A6XXRegs.REG_A7XX_GRAS_UNKNOWN_8008, 0x00000000],
+        [A6XXRegs.REG_A7XX_GRAS_BIN_FOVEAT,    0x00000000],
     ]
 
 add_gpus([
@@ -1185,10 +1185,10 @@ add_gpus([
             [A6XXRegs.REG_A7XX_GRAS_UNKNOWN_8120, 0x09510840],
             [A6XXRegs.REG_A7XX_GRAS_UNKNOWN_8121, 0x00000a62],
 
-            [A6XXRegs.REG_A7XX_GRAS_UNKNOWN_8009, 0x00000000],
-            [A6XXRegs.REG_A7XX_GRAS_UNKNOWN_800A, 0x00000000],
-            [A6XXRegs.REG_A7XX_GRAS_UNKNOWN_800B, 0x00000000],
-            [A6XXRegs.REG_A7XX_GRAS_UNKNOWN_800C, 0x00000000],
+            [A6XXRegs.REG_A7XX_GRAS_BIN_FOVEAT_OFFSET_0, 0x00000000],
+            [A6XXRegs.REG_A7XX_GRAS_BIN_FOVEAT_OFFSET_1, 0x00000000],
+            [A6XXRegs.REG_A7XX_GRAS_BIN_FOVEAT_OFFSET_2, 0x00000000],
+            [A6XXRegs.REG_A7XX_GRAS_BIN_FOVEAT_OFFSET_3, 0x00000000],
 
             [A6XXRegs.REG_A7XX_SP_UNKNOWN_0CE2,   0x00000000],
             [A6XXRegs.REG_A7XX_SP_UNKNOWN_0CE2+1, 0x00000000],
@@ -1201,10 +1201,10 @@ add_gpus([
 
             [A6XXRegs.REG_A7XX_RB_UNKNOWN_8E79,   0x00000000],
             [A6XXRegs.REG_A7XX_RB_UNKNOWN_8899,   0x00000000],
-            [A6XXRegs.REG_A7XX_RB_UNKNOWN_88F5,   0x00000000],
+            [A6XXRegs.REG_A7XX_RB_BIN_FOVEAT,      0x00000000],
             [A6XXRegs.REG_A7XX_RB_UNKNOWN_8C34,   0x00000000],
 
-            [A6XXRegs.REG_A7XX_GRAS_UNKNOWN_8008, 0x00000000],
+            [A6XXRegs.REG_A7XX_GRAS_BIN_FOVEAT,    0x00000000],
         ],
     ))
 
@@ -1268,10 +1268,10 @@ add_gpus([
             [A6XXRegs.REG_A7XX_GRAS_UNKNOWN_8120, 0x09510840],
             [A6XXRegs.REG_A7XX_GRAS_UNKNOWN_8121, 0x00000a62],
 
-            [A6XXRegs.REG_A7XX_GRAS_UNKNOWN_8009, 0x00000000],
-            [A6XXRegs.REG_A7XX_GRAS_UNKNOWN_800A, 0x00000000],
-            [A6XXRegs.REG_A7XX_GRAS_UNKNOWN_800B, 0x00000000],
-            [A6XXRegs.REG_A7XX_GRAS_UNKNOWN_800C, 0x00000000],
+            [A6XXRegs.REG_A7XX_GRAS_BIN_FOVEAT_OFFSET_0, 0x00000000],
+            [A6XXRegs.REG_A7XX_GRAS_BIN_FOVEAT_OFFSET_1, 0x00000000],
+            [A6XXRegs.REG_A7XX_GRAS_BIN_FOVEAT_OFFSET_2, 0x00000000],
+            [A6XXRegs.REG_A7XX_GRAS_BIN_FOVEAT_OFFSET_3, 0x00000000],
 
             [A6XXRegs.REG_A7XX_SP_UNKNOWN_0CE2,   0x00000000],
             [A6XXRegs.REG_A7XX_SP_UNKNOWN_0CE2+1, 0x00000000],
@@ -1284,7 +1284,7 @@ add_gpus([
 
             [A6XXRegs.REG_A7XX_RB_UNKNOWN_8E79,   0x00000000],
             [A6XXRegs.REG_A7XX_RB_UNKNOWN_8899,   0x00000000],
-            [A6XXRegs.REG_A7XX_RB_UNKNOWN_88F5,   0x00000000],
+            [A6XXRegs.REG_A7XX_RB_BIN_FOVEAT,      0x00000000],
         ],
     ))
 
@@ -1372,10 +1372,10 @@ add_gpus([
             [A6XXRegs.REG_A7XX_SP_UNKNOWN_B310, 0x00000000],
             [A6XXRegs.REG_A7XX_GRAS_UNKNOWN_8120, 0x09510840],
             [A6XXRegs.REG_A7XX_GRAS_UNKNOWN_8121, 0x00000a62],
-            [A6XXRegs.REG_A7XX_GRAS_UNKNOWN_8009, 0x00000000],
-            [A6XXRegs.REG_A7XX_GRAS_UNKNOWN_800A, 0x00000000],
-            [A6XXRegs.REG_A7XX_GRAS_UNKNOWN_800B, 0x00000000],
-            [A6XXRegs.REG_A7XX_GRAS_UNKNOWN_800C, 0x00000000],
+            [A6XXRegs.REG_A7XX_GRAS_BIN_FOVEAT_OFFSET_0, 0x00000000],
+            [A6XXRegs.REG_A7XX_GRAS_BIN_FOVEAT_OFFSET_1, 0x00000000],
+            [A6XXRegs.REG_A7XX_GRAS_BIN_FOVEAT_OFFSET_2, 0x00000000],
+            [A6XXRegs.REG_A7XX_GRAS_BIN_FOVEAT_OFFSET_3, 0x00000000],
 
             [A6XXRegs.REG_A7XX_SP_UNKNOWN_0CE2,   0x00000000],
             [A6XXRegs.REG_A7XX_SP_UNKNOWN_0CE2+1, 0x00000000],
@@ -1387,10 +1387,10 @@ add_gpus([
             [A6XXRegs.REG_A7XX_GRAS_UNKNOWN_80A7, 0x00000000],
 
             [A6XXRegs.REG_A7XX_RB_UNKNOWN_8899,   0x00000000],
-            [A6XXRegs.REG_A7XX_RB_UNKNOWN_88F5,   0x00000000],
+            [A6XXRegs.REG_A7XX_RB_BIN_FOVEAT,      0x00000000],
             [A6XXRegs.REG_A7XX_RB_UNKNOWN_8C34,   0x00000000],
 
-            [A6XXRegs.REG_A7XX_GRAS_UNKNOWN_8008, 0x00000000],
+            [A6XXRegs.REG_A7XX_GRAS_BIN_FOVEAT,    0x00000000],
 
             [0x930a, 0],
             [0x960a, 1],
diff --git a/src/freedreno/registers/adreno/a6xx.xml b/src/freedreno/registers/adreno/a6xx.xml
index d22b4f778f8..b895489283d 100644
--- a/src/freedreno/registers/adreno/a6xx.xml
+++ b/src/freedreno/registers/adreno/a6xx.xml
@@ -857,12 +857,48 @@ by a particular renderpass/blit.
 	<!-- Something connected to depth-stencil attachment size -->
 	<reg32 offset="0x8007" name="GRAS_UNKNOWN_8007" variants="A7XX-" usage="rp_blit"/>
 
-	<reg32 offset="0x8008" name="GRAS_UNKNOWN_8008" variants="A7XX-" usage="cmd"/>
+	<!-- the scale/offset is per view, with up to 6 views -->
+	<reg32 offset="0x8008" name="GRAS_BIN_FOVEAT" variants="A7XX-" usage="cmd">
+		<bitfield name="BINSCALEEN" pos="6" type="boolean"/>
+		<enum name="a7xx_bin_scale">
+			<value value="0" name="NOSCALE"/>
+			<value value="1" name="SCALE2X"/>
+			<value value="2" name="SCALE4X"/>
+		</enum>
+		<bitfield name="XSCALE_0" low="8" high="9" type="a7xx_bin_scale"/>
+		<bitfield name="YSCALE_0" low="10" high="11" type="a7xx_bin_scale"/>
+		<bitfield name="XSCALE_1" low="12" high="13" type="a7xx_bin_scale"/>
+		<bitfield name="YSCALE_1" low="14" high="15" type="a7xx_bin_scale"/>
+		<bitfield name="XSCALE_2" low="16" high="17" type="a7xx_bin_scale"/>
+		<bitfield name="YSCALE_2" low="18" high="19" type="a7xx_bin_scale"/>
+		<bitfield name="XSCALE_3" low="20" high="21" type="a7xx_bin_scale"/>
+		<bitfield name="YSCALE_3" low="22" high="23" type="a7xx_bin_scale"/>
+		<bitfield name="XSCALE_4" low="24" high="25" type="a7xx_bin_scale"/>
+		<bitfield name="YSCALE_4" low="26" high="27" type="a7xx_bin_scale"/>
+		<bitfield name="XSCALE_5" low="28" high="29" type="a7xx_bin_scale"/>
+		<bitfield name="YSCALE_5" low="30" high="31" type="a7xx_bin_scale"/>
+	</reg32>
 
-	<reg32 offset="0x8009" name="GRAS_UNKNOWN_8009" variants="A7XX-" usage="cmd"/>
-	<reg32 offset="0x800a" name="GRAS_UNKNOWN_800A" variants="A7XX-" usage="cmd"/>
-	<reg32 offset="0x800b" name="GRAS_UNKNOWN_800B" variants="A7XX-" usage="cmd"/>
-	<reg32 offset="0x800c" name="GRAS_UNKNOWN_800C" variants="A7XX-" usage="cmd"/>
+	<reg32 offset="0x8009" name="GRAS_BIN_FOVEAT_OFFSET_0" variants="A7XX-" usage="cmd">
+		<bitfield name="XOFFSET_0" low="0" high="9" shr="2" type="uint"/>
+		<bitfield name="XOFFSET_1" low="10" high="19" shr="2" type="uint"/>
+		<bitfield name="XOFFSET_2" low="20" high="29" shr="2" type="uint"/>
+	</reg32>
+	<reg32 offset="0x800a" name="GRAS_BIN_FOVEAT_OFFSET_1" variants="A7XX-" usage="cmd">
+		<bitfield name="XOFFSET_3" low="0" high="9" shr="2" type="uint"/>
+		<bitfield name="XOFFSET_4" low="10" high="19" shr="2" type="uint"/>
+		<bitfield name="XOFFSET_5" low="20" high="29" shr="2" type="uint"/>
+	</reg32>
+	<reg32 offset="0x800b" name="GRAS_BIN_FOVEAT_OFFSET_2" variants="A7XX-" usage="cmd">
+		<bitfield name="YOFFSET_0" low="0" high="9" shr="2" type="uint"/>
+		<bitfield name="YOFFSET_1" low="10" high="19" shr="2" type="uint"/>
+		<bitfield name="YOFFSET_2" low="20" high="29" shr="2" type="uint"/>
+	</reg32>
+	<reg32 offset="0x800c" name="GRAS_BIN_FOVEAT_OFFSET_3" variants="A7XX-" usage="cmd">
+		<bitfield name="YOFFSET_3" low="0" high="9" shr="2" type="uint"/>
+		<bitfield name="YOFFSET_4" low="10" high="19" shr="2" type="uint"/>
+		<bitfield name="YOFFSET_5" low="20" high="29" shr="2" type="uint"/>
+	</reg32>
 
 	<!-- <reg32 offset="0x80f0" name="GRAS_UNKNOWN_80F0" type="a6xx_reg_xy"/> -->
 
@@ -1739,8 +1775,9 @@ by a particular renderpass/blit.
 		<bitfield name="ATTACHMENT_FSR_ENABLE" pos="5" type="boolean"/>
 		<bitfield name="PRIMITIVE_FSR_ENABLE" pos="18" type="boolean"/>
 	</reg32>
-	<!-- Connected to VK_EXT_fragment_density_map? -->
-	<reg32 offset="0x88f5" name="RB_UNKNOWN_88F5" variants="A7XX-"/>
+	<reg32 offset="0x88f5" name="RB_BIN_FOVEAT" variants="A7XX-" usage="cmd">
+		<bitfield name="BINSCALEEN" pos="6" type="boolean"/>
+	</reg32>
 	<!-- 0x88f6-0x88ff invalid -->
 	<reg64 offset="0x8900" name="RB_DEPTH_FLAG_BUFFER_BASE" type="waddress" align="64" usage="rp_blit"/>
 	<reg32 offset="0x8902" name="RB_DEPTH_FLAG_BUFFER_PITCH" usage="rp_blit">