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intel/compiler: fine-grained control of dispatch widths

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Reviewed-by: Matt Turner <mattst88@gmail.com> [v1]
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20535>
This commit is contained in:
Marcin Ślusarz
2023-01-05 15:39:28 +01:00
committed by Marge Bot
parent bf3112805c
commit bed18ab3e2
7 changed files with 189 additions and 14 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/intel/dev/intel_debug.c
+71
View File
@@ -41,6 +41,10 @@
uint64_t intel_debug = 0;
#define DEBUG_NO16 (1ull << 16)
#define DEBUG_NO8 (1ull << 20)
#define DEBUG_NO32 (1ull << 39)
static const struct debug_control debug_control[] = {
{ "tex", DEBUG_TEXTURE},
{ "blit", DEBUG_BLIT},
@@ -97,6 +101,26 @@ static const struct debug_control debug_control[] = {
{ NULL, 0 }
};
uint64_t intel_simd = 0;
static const struct debug_control simd_control[] = {
{ "fs8", DEBUG_FS_SIMD8 },
{ "fs16", DEBUG_FS_SIMD16 },
{ "fs32", DEBUG_FS_SIMD32 },
{ "cs8", DEBUG_CS_SIMD8 },
{ "cs16", DEBUG_CS_SIMD16 },
{ "cs32", DEBUG_CS_SIMD32 },
{ "ts8", DEBUG_TS_SIMD8 },
{ "ts16", DEBUG_TS_SIMD16 },
{ "ts32", DEBUG_TS_SIMD32 },
{ "ms8", DEBUG_MS_SIMD8 },
{ "ms16", DEBUG_MS_SIMD16 },
{ "ms32", DEBUG_MS_SIMD32 },
{ "rt8", DEBUG_RT_SIMD8 },
{ "rt16", DEBUG_RT_SIMD16 },
{ "rt32", DEBUG_RT_SIMD32 },
};
uint64_t
intel_debug_flag_for_shader_stage(gl_shader_stage stage)
{
@@ -122,10 +146,57 @@ intel_debug_flag_for_shader_stage(gl_shader_stage stage)
return flags[stage];
}
#define DEBUG_FS_SIMD (DEBUG_FS_SIMD8 | DEBUG_FS_SIMD16 | DEBUG_FS_SIMD32)
#define DEBUG_CS_SIMD (DEBUG_CS_SIMD8 | DEBUG_CS_SIMD16 | DEBUG_CS_SIMD32)
#define DEBUG_TS_SIMD (DEBUG_TS_SIMD8 | DEBUG_TS_SIMD16 | DEBUG_TS_SIMD32)
#define DEBUG_MS_SIMD (DEBUG_MS_SIMD8 | DEBUG_MS_SIMD16 | DEBUG_MS_SIMD32)
#define DEBUG_RT_SIMD (DEBUG_RT_SIMD8 | DEBUG_RT_SIMD16 | DEBUG_RT_SIMD32)
#define DEBUG_SIMD8_ALL \
(DEBUG_FS_SIMD8 | \
DEBUG_CS_SIMD8 | \
DEBUG_TS_SIMD8 | \
DEBUG_MS_SIMD8 | \
DEBUG_RT_SIMD8)
#define DEBUG_SIMD16_ALL \
(DEBUG_FS_SIMD16 | \
DEBUG_CS_SIMD16 | \
DEBUG_TS_SIMD16 | \
DEBUG_MS_SIMD16 | \
DEBUG_RT_SIMD16)
#define DEBUG_SIMD32_ALL \
(DEBUG_FS_SIMD32 | \
DEBUG_CS_SIMD32 | \
DEBUG_TS_SIMD32 | \
DEBUG_MS_SIMD32 | \
DEBUG_RT_SIMD32)
static void
brw_process_intel_debug_variable_once(void)
{
intel_debug = parse_debug_string(getenv("INTEL_DEBUG"), debug_control);
intel_simd = parse_debug_string(getenv("INTEL_SIMD_DEBUG"), simd_control);
if (!(intel_simd & DEBUG_FS_SIMD))
intel_simd |= DEBUG_FS_SIMD;
if (!(intel_simd & DEBUG_CS_SIMD))
intel_simd |= DEBUG_CS_SIMD;
if (!(intel_simd & DEBUG_TS_SIMD))
intel_simd |= DEBUG_TS_SIMD;
if (!(intel_simd & DEBUG_MS_SIMD))
intel_simd |= DEBUG_MS_SIMD;
if (!(intel_simd & DEBUG_RT_SIMD))
intel_simd |= DEBUG_RT_SIMD;
if (intel_debug & DEBUG_NO8)
intel_simd &= ~DEBUG_SIMD8_ALL;
if (intel_debug & DEBUG_NO16)
intel_simd &= ~DEBUG_SIMD16_ALL;
if (intel_debug & DEBUG_NO32)
intel_simd &= ~DEBUG_SIMD32_ALL;
intel_debug &= ~(DEBUG_NO8 | DEBUG_NO16 | DEBUG_NO32);
}
void
src/intel/dev/intel_debug.h
+35 -6
View File
@@ -61,11 +61,13 @@ extern uint64_t intel_debug;
#define DEBUG_CLIP (1ull << 13)
#define DEBUG_STALL (1ull << 14)
#define DEBUG_BLORP (1ull << 15)
#define DEBUG_NO16 (1ull << 16)
/* internal to intel_debug.c, replaced by INTEL_SIMD */
/*#define DEBUG_NO16 (1ull << 16)*/
#define DEBUG_NO_DUAL_OBJECT_GS (1ull << 17)
#define DEBUG_OPTIMIZER (1ull << 18)
#define DEBUG_ANNOTATION (1ull << 19)
#define DEBUG_NO8 (1ull << 20)
/* internal to intel_debug.c, replaced by INTEL_SIMD */
/*#define DEBUG_NO8 (1ull << 20)*/
#define DEBUG_NO_OACONFIG (1ull << 21)
#define DEBUG_SPILL_FS (1ull << 22)
#define DEBUG_SPILL_VEC4 (1ull << 23)
@@ -84,7 +86,8 @@ extern uint64_t intel_debug;
#define DEBUG_BT (1ull << 36)
#define DEBUG_PIPE_CONTROL (1ull << 37)
#define DEBUG_NO_FAST_CLEAR (1ull << 38)
#define DEBUG_NO32 (1ull << 39)
/* internal to intel_debug.c, replaced by INTEL_SIMD */
/*#define DEBUG_NO32 (1ull << 39)*/
#define DEBUG_RT (1ull << 40)
#define DEBUG_TASK (1ull << 41)
#define DEBUG_MESH (1ull << 42)
@@ -97,9 +100,35 @@ extern uint64_t intel_debug;
/* These flags may affect program generation */
#define DEBUG_DISK_CACHE_MASK \
(DEBUG_NO16 | DEBUG_NO_DUAL_OBJECT_GS | DEBUG_NO8 | DEBUG_SPILL_FS | \
DEBUG_SPILL_VEC4 | DEBUG_NO_COMPACTION | DEBUG_DO32 | DEBUG_SOFT64 | \
DEBUG_NO32)
(DEBUG_NO_DUAL_OBJECT_GS | DEBUG_SPILL_FS | \
DEBUG_SPILL_VEC4 | DEBUG_NO_COMPACTION | DEBUG_DO32 | DEBUG_SOFT64)
extern uint64_t intel_simd;
#define INTEL_SIMD(type, size) (!!(intel_simd & (DEBUG_ ## type ## _SIMD ## size)))
/* VS, TCS, TES and GS stages are dispatched in one size */
#define DEBUG_FS_SIMD8 (1ull << 0)
#define DEBUG_FS_SIMD16 (1ull << 1)
#define DEBUG_FS_SIMD32 (1ull << 2)
#define DEBUG_CS_SIMD8 (1ull << 3)
#define DEBUG_CS_SIMD16 (1ull << 4)
#define DEBUG_CS_SIMD32 (1ull << 5)
#define DEBUG_TS_SIMD8 (1ull << 6)
#define DEBUG_TS_SIMD16 (1ull << 7)
#define DEBUG_TS_SIMD32 (1ull << 8)
#define DEBUG_MS_SIMD8 (1ull << 9)
#define DEBUG_MS_SIMD16 (1ull << 10)
#define DEBUG_MS_SIMD32 (1ull << 11)
#define DEBUG_RT_SIMD8 (1ull << 12)
#define DEBUG_RT_SIMD16 (1ull << 13)
#define DEBUG_RT_SIMD32 (1ull << 14)
#define SIMD_DISK_CACHE_MASK ((1ull << 15) - 1)
#ifdef HAVE_ANDROID_PLATFORM
#define LOG_TAG "INTEL-MESA"