From bec7b7d52818f2985eb599f8d6c745bf50f5c518 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Thu, 4 Feb 2021 01:17:19 -0500 Subject: [PATCH] ac/gpu_info: remove redundant radeon_info::num_sdp_interfaces Reviewed-by: Bas Nieuwenhuizen Reviewed-by: Pierre-Eric Pelloux-Prayer Part-of: --- src/amd/common/ac_gpu_info.c | 5 ----- src/amd/common/ac_gpu_info.h | 1 - src/amd/vulkan/radv_pipeline.c | 2 +- src/gallium/drivers/radeonsi/si_state_binning.c | 2 +- 4 files changed, 2 insertions(+), 8 deletions(-) diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c index 6924e57572c..7d75727d71b 100644 --- a/src/amd/common/ac_gpu_info.c +++ b/src/amd/common/ac_gpu_info.c @@ -929,10 +929,6 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info, } } - /* The number of SDPs is the same as the number of TCCs for now. */ - if (info->chip_class >= GFX10) - info->num_sdp_interfaces = info->num_tcc_blocks; - if (info->chip_class >= GFX10_3) info->max_wave64_per_simd = 16; else if (info->chip_class == GFX10) @@ -1062,7 +1058,6 @@ void ac_print_gpu_info(struct radeon_info *info, FILE *f) fprintf(f, " has_dedicated_vram = %u\n", info->has_dedicated_vram); fprintf(f, " all_vram_visible = %u\n", info->all_vram_visible); fprintf(f, " smart_access_memory = %u\n", info->smart_access_memory); - fprintf(f, " num_sdp_interfaces = %u\n", info->num_sdp_interfaces); fprintf(f, " max_tcc_blocks = %i\n", info->max_tcc_blocks); fprintf(f, " num_tcc_blocks = %i\n", info->num_tcc_blocks); fprintf(f, " tcc_cache_line_size = %u\n", info->tcc_cache_line_size); diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h index e644e527aea..3f9cde55732 100644 --- a/src/amd/common/ac_gpu_info.h +++ b/src/amd/common/ac_gpu_info.h @@ -104,7 +104,6 @@ struct radeon_info { bool smart_access_memory; bool has_l2_uncached; bool r600_has_virtual_memory; - uint32_t num_sdp_interfaces; uint32_t max_tcc_blocks; uint32_t num_tcc_blocks; uint32_t tcc_cache_line_size; diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index e9831c72e80..c4c4af11871 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -3935,7 +3935,7 @@ radv_gfx10_compute_bin_size(const struct radv_pipeline *pipeline, const VkGraphi const unsigned fmask_tag_count = 44; const unsigned rb_count = pipeline->device->physical_device->rad_info.max_render_backends; - const unsigned pipe_count = MAX2(rb_count, pipeline->device->physical_device->rad_info.num_sdp_interfaces); + const unsigned pipe_count = MAX2(rb_count, pipeline->device->physical_device->rad_info.num_tcc_blocks); const unsigned db_tag_part = (db_tag_count * rb_count / pipe_count) * db_tag_size * pipe_count; const unsigned color_tag_part = (color_tag_count * rb_count / pipe_count) * color_tag_size * pipe_count; diff --git a/src/gallium/drivers/radeonsi/si_state_binning.c b/src/gallium/drivers/radeonsi/si_state_binning.c index f9e4b273317..96354eff79f 100644 --- a/src/gallium/drivers/radeonsi/si_state_binning.c +++ b/src/gallium/drivers/radeonsi/si_state_binning.c @@ -310,7 +310,7 @@ static void gfx10_get_bin_sizes(struct si_context *sctx, unsigned cb_target_enab const unsigned FcReadTags = 44; const unsigned num_rbs = sctx->screen->info.max_render_backends; - const unsigned num_pipes = MAX2(num_rbs, sctx->screen->info.num_sdp_interfaces); + const unsigned num_pipes = MAX2(num_rbs, sctx->screen->info.num_tcc_blocks); const unsigned depthBinSizeTagPart = ((ZsNumTags * num_rbs / num_pipes) * (ZsTagSize * num_pipes));