From be8977811b9885dbac7aad9c75a00da85a620972 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Fri, 11 Apr 2025 01:57:57 -0400 Subject: [PATCH] ac/nir: remove shader_info parameter from ac_nir_compute_tess_wg_info MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reviewed-by: Pierre-Eric Pelloux-Prayer Reviewed-by: Timur Kristóf Part-of: --- src/amd/common/nir/ac_nir.h | 3 ++- src/amd/common/nir/ac_nir_lower_tess_io_to_mem.c | 11 ++++++----- src/amd/vulkan/radv_shader.c | 8 +++++--- src/gallium/drivers/radeonsi/si_state_shaders.cpp | 5 ++++- 4 files changed, 17 insertions(+), 10 deletions(-) diff --git a/src/amd/common/nir/ac_nir.h b/src/amd/common/nir/ac_nir.h index 1e4e13fae03..e78f43bfcaf 100644 --- a/src/amd/common/nir/ac_nir.h +++ b/src/amd/common/nir/ac_nir.h @@ -118,7 +118,8 @@ ac_nir_lower_tes_inputs_to_mem(nir_shader *shader, ac_nir_map_io_driver_location map); void -ac_nir_compute_tess_wg_info(const struct radeon_info *info, const struct shader_info *tcs_info, +ac_nir_compute_tess_wg_info(const struct radeon_info *info, uint64_t outputs_read, uint64_t outputs_written, + uint32_t patch_outputs_read, uint32_t patch_outputs_written, unsigned tcs_vertices_out, unsigned wave_size, bool tess_uses_primid, bool all_invocations_define_tess_levels, unsigned num_tcs_input_cp, unsigned lds_input_vertex_size, unsigned num_mem_tcs_outputs, unsigned num_mem_tcs_patch_outputs, diff --git a/src/amd/common/nir/ac_nir_lower_tess_io_to_mem.c b/src/amd/common/nir/ac_nir_lower_tess_io_to_mem.c index cfe943aa130..e018d53f2e1 100644 --- a/src/amd/common/nir/ac_nir_lower_tess_io_to_mem.c +++ b/src/amd/common/nir/ac_nir_lower_tess_io_to_mem.c @@ -1289,19 +1289,20 @@ ac_nir_lower_tes_inputs_to_mem(nir_shader *shader, } void -ac_nir_compute_tess_wg_info(const struct radeon_info *info, const struct shader_info *tcs_info, +ac_nir_compute_tess_wg_info(const struct radeon_info *info, uint64_t outputs_read, uint64_t outputs_written, + uint32_t patch_outputs_read, uint32_t patch_outputs_written, unsigned tcs_vertices_out, unsigned wave_size, bool tess_uses_primid, bool all_invocations_define_tess_levels, unsigned num_tcs_input_cp, unsigned lds_input_vertex_size, unsigned num_mem_tcs_outputs, unsigned num_mem_tcs_patch_outputs, unsigned *num_patches_per_wg, unsigned *hw_lds_size) { - unsigned num_tcs_output_cp = tcs_info->tess.tcs_vertices_out; + unsigned num_tcs_output_cp = tcs_vertices_out; unsigned lds_output_vertex_size = - util_bitcount64(tcs_info->outputs_read & tcs_info->outputs_written & ~TESS_LVL_MASK) * 16; + util_bitcount64(outputs_read & outputs_written & ~TESS_LVL_MASK) * 16; unsigned lds_perpatch_output_patch_size = (util_bitcount64(all_invocations_define_tess_levels ? - 0 : tcs_info->outputs_written & TESS_LVL_MASK) + - util_bitcount(tcs_info->patch_outputs_read & tcs_info->patch_outputs_written)) * 16; + 0 : outputs_written & TESS_LVL_MASK) + + util_bitcount(patch_outputs_read & patch_outputs_written)) * 16; unsigned lds_per_patch = num_tcs_input_cp * lds_input_vertex_size + num_tcs_output_cp * lds_output_vertex_size + diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c index 69f28a89172..afe7c5ed280 100644 --- a/src/amd/vulkan/radv_shader.c +++ b/src/amd/vulkan/radv_shader.c @@ -3604,9 +3604,11 @@ radv_get_tess_wg_info(const struct radv_physical_device *pdev, const struct shad { const uint32_t lds_input_vertex_size = get_tcs_input_vertex_stride(tcs_num_lds_inputs); - ac_nir_compute_tess_wg_info(&pdev->info, tcs_info, pdev->ge_wave_size, false, all_invocations_define_tess_levels, - tcs_num_input_vertices, lds_input_vertex_size, tcs_num_vram_outputs, - tcs_num_vram_patch_outputs, num_patches_per_wg, hw_lds_size); + ac_nir_compute_tess_wg_info(&pdev->info, tcs_info->outputs_read, tcs_info->outputs_written, + tcs_info->patch_outputs_read, tcs_info->patch_outputs_written, + tcs_info->tess.tcs_vertices_out, pdev->ge_wave_size, false, + all_invocations_define_tess_levels, tcs_num_input_vertices, lds_input_vertex_size, + tcs_num_vram_outputs, tcs_num_vram_patch_outputs, num_patches_per_wg, hw_lds_size); } VkResult diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.cpp b/src/gallium/drivers/radeonsi/si_state_shaders.cpp index 34f4945dde1..b8f22d23f32 100644 --- a/src/gallium/drivers/radeonsi/si_state_shaders.cpp +++ b/src/gallium/drivers/radeonsi/si_state_shaders.cpp @@ -4806,7 +4806,10 @@ void si_update_tess_io_layout_state(struct si_context *sctx) unsigned num_patches, lds_size; /* Compute NUM_PATCHES and LDS_SIZE. */ - ac_nir_compute_tess_wg_info(&sctx->screen->info, &tcs->info.base, ls_current->wave_size, + ac_nir_compute_tess_wg_info(&sctx->screen->info, tcs->info.base.outputs_read, + tcs->info.base.outputs_written, tcs->info.base.patch_outputs_read, + tcs->info.base.patch_outputs_written, + tcs->info.base.tess.tcs_vertices_out, ls_current->wave_size, tess_uses_primid, tcs->info.tessfactors_are_def_in_all_invocs, num_tcs_input_cp, lds_input_vertex_size, num_mem_tcs_outputs, num_mem_tcs_patch_outputs,