From be49b02f0517d38a9445039789eebe1e0f7dcc73 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Mon, 27 May 2024 20:36:37 +0200 Subject: [PATCH] radv: Properly link TCS->TES IO again. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This commit makes RADV TCS->TES IO great again. Fossil DB stats on Navi 21: Totals from 2634 (3.32% of 79395) affected shaders: MaxWaves: 56336 -> 56450 (+0.20%) Instrs: 1670370 -> 1667819 (-0.15%); split: -0.22%, +0.06% CodeSize: 8675476 -> 8643176 (-0.37%); split: -0.39%, +0.01% VGPRs: 126776 -> 126608 (-0.13%) LDS: 10444288 -> 10617856 (+1.66%) Inputs: 30910 -> 25426 (-17.74%) Outputs: 27000 -> 21516 (-20.31%) Latency: 9403584 -> 9391648 (-0.13%); split: -0.25%, +0.12% InvThroughput: 2127488 -> 2127180 (-0.01%); split: -0.13%, +0.12% VClause: 33495 -> 34413 (+2.74%); split: -0.32%, +3.06% SClause: 27905 -> 27879 (-0.09%); split: -0.30%, +0.20% Copies: 82562 -> 83007 (+0.54%); split: -0.32%, +0.86% PreSGPRs: 91029 -> 91014 (-0.02%) PreVGPRs: 108505 -> 108473 (-0.03%); split: -0.06%, +0.03% VALU: 1088113 -> 1087730 (-0.04%); split: -0.18%, +0.14% SALU: 182853 -> 179541 (-1.81%); split: -1.82%, +0.01% Signed-off-by: Timur Kristóf Reviewed-by: Samuel Pitoiset Part-of: --- src/amd/vulkan/nir/radv_nir_lower_io.c | 4 ++-- src/amd/vulkan/radv_pipeline_graphics.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/amd/vulkan/nir/radv_nir_lower_io.c b/src/amd/vulkan/nir/radv_nir_lower_io.c index d0e21786d6a..82d7e0a3da3 100644 --- a/src/amd/vulkan/nir/radv_nir_lower_io.c +++ b/src/amd/vulkan/nir/radv_nir_lower_io.c @@ -142,12 +142,12 @@ radv_nir_lower_io_to_mem(struct radv_device *device, struct radv_shader_stage *s } } else if (nir->info.stage == MESA_SHADER_TESS_CTRL) { NIR_PASS_V(nir, ac_nir_lower_hs_inputs_to_mem, map_input, info->vs.tcs_in_out_eq); - NIR_PASS_V(nir, ac_nir_lower_hs_outputs_to_mem, radv_map_io_driver_location, pdev->info.gfx_level, + NIR_PASS_V(nir, ac_nir_lower_hs_outputs_to_mem, map_output, pdev->info.gfx_level, info->tcs.tes_inputs_read, info->tcs.tes_patch_inputs_read, info->wave_size, false, false); return true; } else if (nir->info.stage == MESA_SHADER_TESS_EVAL) { - NIR_PASS_V(nir, ac_nir_lower_tes_inputs_to_mem, radv_map_io_driver_location); + NIR_PASS_V(nir, ac_nir_lower_tes_inputs_to_mem, map_input); if (info->tes.as_es) { NIR_PASS_V(nir, ac_nir_lower_es_outputs_to_mem, map_output, pdev->info.gfx_level, info->esgs_itemsize); diff --git a/src/amd/vulkan/radv_pipeline_graphics.c b/src/amd/vulkan/radv_pipeline_graphics.c index 86a59742210..c9eedf5a16b 100644 --- a/src/amd/vulkan/radv_pipeline_graphics.c +++ b/src/amd/vulkan/radv_pipeline_graphics.c @@ -1382,7 +1382,7 @@ radv_link_tcs(const struct radv_device *device, struct radv_shader_stage *tcs_st const uint64_t nir_mask = tcs_stage->nir->info.outputs_written & tes_stage->nir->info.inputs_read & ~(VARYING_BIT_TESS_LEVEL_OUTER | VARYING_BIT_TESS_LEVEL_INNER); const uint64_t io_mask = radv_gather_unlinked_io_mask(nir_mask); - const unsigned num_reserved_outputs = util_last_bit64(io_mask); + const unsigned num_reserved_outputs = util_bitcount64(io_mask); /* Count the number of per-patch output slots we need to reserve for the TCS and TES. * This is necessary because we need it to determine the patch size in VRAM. @@ -1390,7 +1390,7 @@ radv_link_tcs(const struct radv_device *device, struct radv_shader_stage *tcs_st const uint64_t patch_io_mask = radv_gather_unlinked_patch_io_mask( tcs_stage->nir->info.outputs_written & tes_stage->nir->info.inputs_read, tcs_stage->nir->info.patch_outputs_written & tes_stage->nir->info.patch_inputs_read); - const unsigned num_reserved_patch_outputs = util_last_bit64(patch_io_mask); + const unsigned num_reserved_patch_outputs = util_bitcount64(patch_io_mask); tcs_stage->info.tcs.num_linked_outputs = num_reserved_outputs; tcs_stage->info.tcs.num_linked_patch_outputs = num_reserved_patch_outputs;