From bdec044c880ef38fad3641d306b9828e3c871003 Mon Sep 17 00:00:00 2001 From: Konstantin Seurer Date: Sun, 16 Jul 2023 12:16:38 +0200 Subject: [PATCH] aco: Do not fixup registers if there are no shader calls MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Frees up some registers when using monolithic compilation. Quake II RTX and Control (with monolithic compilation): Totals from 10 (29.41% of 34) affected shaders: MaxWaves: 77 -> 98 (+27.27%) Instrs: 49047 -> 48984 (-0.13%); split: -0.16%, +0.03% CodeSize: 260420 -> 259880 (-0.21%); split: -0.25%, +0.04% VGPRs: 1328 -> 1104 (-16.87%) Latency: 477134 -> 479377 (+0.47%); split: -0.05%, +0.52% InvThroughput: 137763 -> 114108 (-17.17%) VClause: 1318 -> 1286 (-2.43%); split: -2.66%, +0.23% SClause: 1295 -> 1293 (-0.15%); split: -0.54%, +0.39% Copies: 7838 -> 7782 (-0.71%); split: -0.82%, +0.10% Branches: 2592 -> 2589 (-0.12%) PreSGPRs: 874 -> 796 (-8.92%) PreVGPRs: 1283 -> 1013 (-21.04%) Reviewed-by: Daniel Schürmann Part-of: --- .../compiler/aco_instruction_selection.cpp | 48 ++++++++++++------- 1 file changed, 30 insertions(+), 18 deletions(-) diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp index 25e3b565256..ab7b1891cd2 100644 --- a/src/amd/compiler/aco_instruction_selection.cpp +++ b/src/amd/compiler/aco_instruction_selection.cpp @@ -11272,6 +11272,31 @@ merged_wave_info_to_mask(isel_context* ctx, unsigned i) return lanecount_to_mask(ctx, count); } +static void +insert_rt_jump_next(isel_context& ctx, const struct ac_shader_args* args) +{ + append_logical_end(ctx.block); + ctx.block->kind |= block_kind_uniform; + + unsigned src_count = ctx.args->arg_count; + Pseudo_instruction* ret = + create_instruction(aco_opcode::p_return, Format::PSEUDO, src_count, 0); + ctx.block->instructions.emplace_back(ret); + + for (unsigned i = 0; i < src_count; i++) { + enum ac_arg_regfile file = ctx.args->args[i].file; + unsigned size = ctx.args->args[i].size; + unsigned reg = ctx.args->args[i].offset + (file == AC_ARG_SGPR ? 0 : 256); + RegClass type = RegClass(file == AC_ARG_SGPR ? RegType::sgpr : RegType::vgpr, size); + Operand op = ctx.arg_temps[i].id() ? Operand(ctx.arg_temps[i], PhysReg{reg}) + : Operand(PhysReg{reg}, type); + ret->operands[i] = op; + } + + Builder bld(ctx.program, ctx.block); + bld.sop1(aco_opcode::s_setpc_b64, get_arg(&ctx, ctx.args->rt.uniform_shader_addr)); +} + void select_program_rt(isel_context& ctx, unsigned shader_count, struct nir_shader* const* shaders, const struct ac_shader_args* args) @@ -11291,24 +11316,11 @@ select_program_rt(isel_context& ctx, unsigned shader_count, struct nir_shader* c split_arguments(&ctx, startpgm); visit_cf_list(&ctx, &nir_shader_get_entrypoint(nir)->body); - /* Fix output registers and jump to next shader */ - append_logical_end(ctx.block); - ctx.block->kind |= block_kind_uniform; - Builder bld(ctx.program, ctx.block); - unsigned src_count = ctx.args->arg_count; - Pseudo_instruction* ret = - create_instruction(aco_opcode::p_return, Format::PSEUDO, src_count, 0); - ctx.block->instructions.emplace_back(ret); - for (unsigned j = 0; j < src_count; j++) { - enum ac_arg_regfile file = ctx.args->args[j].file; - unsigned size = ctx.args->args[j].size; - unsigned reg = ctx.args->args[j].offset + (file == AC_ARG_SGPR ? 0 : 256); - RegClass type = RegClass(file == AC_ARG_SGPR ? RegType::sgpr : RegType::vgpr, size); - Operand op = ctx.arg_temps[j].id() ? Operand(ctx.arg_temps[j], PhysReg{reg}) - : Operand(PhysReg{reg}, type); - ret->operands[j] = op; - } - bld.sop1(aco_opcode::s_setpc_b64, get_arg(&ctx, ctx.args->rt.uniform_shader_addr)); + /* Fix output registers and jump to next shader. We can skip this when dealing with a raygen + * shader without shader calls. + */ + if (shader_count > 1 || shaders[i]->info.stage != MESA_SHADER_RAYGEN) + insert_rt_jump_next(ctx, args); cleanup_context(&ctx); }