From bddd7919d3844b8397c5d455a1ff23e0c4289241 Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Wed, 22 Oct 2025 15:33:34 +0200 Subject: [PATCH] amd,radv,radeonsi: add ac_buffered_sh_regs Signed-off-by: Samuel Pitoiset Part-of: --- src/amd/common/ac_cmdbuf.h | 14 ++++++++ src/amd/vulkan/radv_cmd_buffer.h | 5 +-- src/amd/vulkan/radv_cs.c | 2 +- src/amd/vulkan/radv_cs.h | 14 ++++---- src/gallium/drivers/radeonsi/si_build_pm4.h | 24 +++++++------- src/gallium/drivers/radeonsi/si_gfx_cs.c | 8 ++--- src/gallium/drivers/radeonsi/si_pipe.h | 17 ++-------- .../drivers/radeonsi/si_state_draw.cpp | 32 +++++++++---------- 8 files changed, 58 insertions(+), 58 deletions(-) diff --git a/src/amd/common/ac_cmdbuf.h b/src/amd/common/ac_cmdbuf.h index 716e1333e01..35eb7254837 100644 --- a/src/amd/common/ac_cmdbuf.h +++ b/src/amd/common/ac_cmdbuf.h @@ -42,6 +42,20 @@ struct ac_gfx12_reg { uint32_t reg_value; }; +/* GFX11+: Buffered SH registers for SET_SH_REG_PAIRS_*. */ +struct ac_buffered_sh_regs { + uint32_t num; + union { + struct { + struct ac_gfx11_reg_pair regs[32]; + } gfx11; + + struct { + struct ac_gfx12_reg regs[256]; + } gfx12; + }; +}; + #define ac_cmdbuf_begin(cs) struct ac_cmdbuf *__cs = (cs); \ uint32_t __cs_num = __cs->cdw; \ UNUSED uint32_t __cs_num_initial = __cs_num; \ diff --git a/src/amd/vulkan/radv_cmd_buffer.h b/src/amd/vulkan/radv_cmd_buffer.h index 948e09a17e0..b4101b8fdb7 100644 --- a/src/amd/vulkan/radv_cmd_buffer.h +++ b/src/amd/vulkan/radv_cmd_buffer.h @@ -581,10 +581,7 @@ struct radv_cmd_stream { struct radv_tracked_regs tracked_regs; enum amd_ip_type hw_ip; - uint32_t num_buffered_sh_regs; - struct { - struct ac_gfx12_reg buffered_sh_regs[256]; - } gfx12; + struct ac_buffered_sh_regs buffered_sh_regs; }; struct radv_cmd_buffer { diff --git a/src/amd/vulkan/radv_cs.c b/src/amd/vulkan/radv_cs.c index 44ac4561cfa..93edae1410a 100644 --- a/src/amd/vulkan/radv_cs.c +++ b/src/amd/vulkan/radv_cs.c @@ -459,7 +459,7 @@ void radv_init_cmd_stream(struct radv_cmd_stream *cs, const enum amd_ip_type ip_type) { cs->context_roll_without_scissor_emitted = false; - cs->num_buffered_sh_regs = 0; + cs->buffered_sh_regs.num = 0; cs->hw_ip = ip_type; radv_init_tracked_regs(cs); diff --git a/src/amd/vulkan/radv_cs.h b/src/amd/vulkan/radv_cs.h index 8a52f64c158..447359065cb 100644 --- a/src/amd/vulkan/radv_cs.h +++ b/src/amd/vulkan/radv_cs.h @@ -239,10 +239,10 @@ radeon_check_space(struct radeon_winsys *ws, struct ac_cmdbuf *cs, unsigned need /* GFX12 generic packet building helpers for buffered registers. Don't use these directly. */ #define __gfx12_push_reg(reg, value, base_offset) \ do { \ - unsigned __i = __rcs->num_buffered_sh_regs++; \ - assert(__i < ARRAY_SIZE(__rcs->gfx12.buffered_sh_regs)); \ - __rcs->gfx12.buffered_sh_regs[__i].reg_offset = ((reg) - (base_offset)) >> 2; \ - __rcs->gfx12.buffered_sh_regs[__i].reg_value = value; \ + unsigned __i = __rcs->buffered_sh_regs.num++; \ + assert(__i < ARRAY_SIZE(__rcs->buffered_sh_regs.gfx12.regs)); \ + __rcs->buffered_sh_regs.gfx12.regs[__i].reg_offset = ((reg) - (base_offset)) >> 2; \ + __rcs->buffered_sh_regs.gfx12.regs[__i].reg_value = value; \ } while (0) /* GFX12 packet building helpers for PAIRS packets. */ @@ -275,7 +275,7 @@ radeon_check_space(struct radeon_winsys *ws, struct ac_cmdbuf *cs, unsigned need ALWAYS_INLINE static void radv_gfx12_emit_buffered_regs(struct radv_device *device, struct radv_cmd_stream *cs) { - const uint32_t reg_count = cs->num_buffered_sh_regs; + const uint32_t reg_count = cs->buffered_sh_regs.num; if (!reg_count) return; @@ -284,10 +284,10 @@ radv_gfx12_emit_buffered_regs(struct radv_device *device, struct radv_cmd_stream radeon_begin(cs); radeon_emit(PKT3(PKT3_SET_SH_REG_PAIRS, reg_count * 2 - 1, 0) | PKT3_RESET_FILTER_CAM_S(1)); - radeon_emit_array(cs->gfx12.buffered_sh_regs, reg_count * 2); + radeon_emit_array(cs->buffered_sh_regs.gfx12.regs, reg_count * 2); radeon_end(); - cs->num_buffered_sh_regs = 0; + cs->buffered_sh_regs.num = 0; } ALWAYS_INLINE static void diff --git a/src/gallium/drivers/radeonsi/si_build_pm4.h b/src/gallium/drivers/radeonsi/si_build_pm4.h index 205c0695b8b..b37d1449dd9 100644 --- a/src/gallium/drivers/radeonsi/si_build_pm4.h +++ b/src/gallium/drivers/radeonsi/si_build_pm4.h @@ -333,20 +333,20 @@ /* GFX11 packet building helpers for buffered SH registers. */ #define gfx11_push_gfx_sh_reg(reg, value) \ - gfx11_push_reg(reg, value, SI_SH, sctx->gfx11.buffered_gfx_sh_regs, \ - sctx->num_buffered_gfx_sh_regs) + gfx11_push_reg(reg, value, SI_SH, sctx->buffered_gfx_sh_regs.gfx11.regs, \ + sctx->buffered_gfx_sh_regs.num) #define gfx11_push_compute_sh_reg(reg, value) \ - gfx11_push_reg(reg, value, SI_SH, sctx->gfx11.buffered_compute_sh_regs, \ - sctx->num_buffered_compute_sh_regs) + gfx11_push_reg(reg, value, SI_SH, sctx->buffered_compute_sh_regs.gfx11.regs, \ + sctx->buffered_compute_sh_regs.num) #define gfx11_opt_push_gfx_sh_reg(reg, reg_enum, value) \ - gfx11_opt_push_reg(reg, reg_enum, value, SI_SH, sctx->gfx11.buffered_gfx_sh_regs, \ - sctx->num_buffered_gfx_sh_regs) + gfx11_opt_push_reg(reg, reg_enum, value, SI_SH, sctx->buffered_gfx_sh_regs.gfx11.regs, \ + sctx->buffered_gfx_sh_regs.num) #define gfx11_opt_push_compute_sh_reg(reg, reg_enum, value) \ - gfx11_opt_push_reg(reg, reg_enum, value, SI_SH, sctx->gfx11.buffered_compute_sh_regs, \ - sctx->num_buffered_compute_sh_regs) + gfx11_opt_push_reg(reg, reg_enum, value, SI_SH, sctx->buffered_compute_sh_regs.gfx11.regs, \ + sctx->buffered_compute_sh_regs.num) /* GFX11 packet building helpers for SET_CONTEXT_REG_PAIRS_PACKED. * Registers are buffered on the stack and then copied to the command buffer at the end. @@ -422,10 +422,10 @@ /* GFX12 generic packet building helpers for buffered registers. Don't use these directly. */ #define gfx12_push_reg(reg, value, base_offset, type) do { \ - unsigned __i = sctx->num_buffered_##type##_regs++; \ - assert(__i < ARRAY_SIZE(sctx->gfx12.buffered_##type##_regs)); \ - sctx->gfx12.buffered_##type##_regs[__i].reg_offset = ((reg) - (base_offset)) >> 2; \ - sctx->gfx12.buffered_##type##_regs[__i].reg_value = value; \ + unsigned __i = sctx->buffered_##type##_regs.num++; \ + assert(__i < ARRAY_SIZE(sctx->buffered_##type##_regs.gfx12.regs)); \ + sctx->buffered_##type##_regs.gfx12.regs[__i].reg_offset = ((reg) - (base_offset)) >> 2; \ + sctx->buffered_##type##_regs.gfx12.regs[__i].reg_value = value; \ } while (0) #define gfx12_opt_push_reg(reg, reg_enum, value, type) do { \ diff --git a/src/gallium/drivers/radeonsi/si_gfx_cs.c b/src/gallium/drivers/radeonsi/si_gfx_cs.c index 937f1e685a2..e9a577a9b36 100644 --- a/src/gallium/drivers/radeonsi/si_gfx_cs.c +++ b/src/gallium/drivers/radeonsi/si_gfx_cs.c @@ -651,10 +651,10 @@ void si_begin_new_gfx_cs(struct si_context *ctx, bool first_cs) ctx->last_tes_sh_base = -1; ctx->last_num_tcs_input_cp = -1; - assert(ctx->num_buffered_gfx_sh_regs == 0); - assert(ctx->num_buffered_compute_sh_regs == 0); - ctx->num_buffered_gfx_sh_regs = 0; - ctx->num_buffered_compute_sh_regs = 0; + assert(ctx->buffered_gfx_sh_regs.num == 0); + assert(ctx->buffered_compute_sh_regs.num == 0); + ctx->buffered_gfx_sh_regs.num = 0; + ctx->buffered_compute_sh_regs.num = 0; if (ctx->scratch_buffer) si_mark_atom_dirty(ctx, &ctx->atoms.s.scratch_state); diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h index 68643033510..707f053f872 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.h +++ b/src/gallium/drivers/radeonsi/si_pipe.h @@ -1030,20 +1030,9 @@ struct si_context { union si_state queued; union si_state emitted; - /* Gfx11+: Buffered SH registers for SET_SH_REG_PAIRS_*. */ - unsigned num_buffered_gfx_sh_regs; - unsigned num_buffered_compute_sh_regs; - union { - struct { - struct ac_gfx11_reg_pair buffered_gfx_sh_regs[32]; - struct ac_gfx11_reg_pair buffered_compute_sh_regs[32]; - } gfx11; - - struct { - struct ac_gfx12_reg buffered_gfx_sh_regs[64]; - struct ac_gfx12_reg buffered_compute_sh_regs[64]; - } gfx12; - }; + /* Buffered registers (GFX11+). */ + struct ac_buffered_sh_regs buffered_gfx_sh_regs; + struct ac_buffered_sh_regs buffered_compute_sh_regs; /* Atom declarations. */ struct si_framebuffer framebuffer; diff --git a/src/gallium/drivers/radeonsi/si_state_draw.cpp b/src/gallium/drivers/radeonsi/si_state_draw.cpp index ba2032e5091..68c06a7ac21 100644 --- a/src/gallium/drivers/radeonsi/si_state_draw.cpp +++ b/src/gallium/drivers/radeonsi/si_state_draw.cpp @@ -1265,12 +1265,12 @@ void si_emit_buffered_compute_sh_regs(struct si_context *sctx) { if (sctx->gfx_level >= GFX12) { radeon_begin(&sctx->gfx_cs); - gfx12_emit_buffered_sh_regs_inline(&sctx->num_buffered_compute_sh_regs, - sctx->gfx12.buffered_compute_sh_regs); + gfx12_emit_buffered_sh_regs_inline(&sctx->buffered_compute_sh_regs.num, + sctx->buffered_compute_sh_regs.gfx12.regs); radeon_end(); } else { - gfx11_emit_buffered_sh_regs_inline(sctx, &sctx->num_buffered_compute_sh_regs, - sctx->gfx11.buffered_compute_sh_regs); + gfx11_emit_buffered_sh_regs_inline(sctx, &sctx->buffered_compute_sh_regs.num, + sctx->buffered_compute_sh_regs.gfx11.regs); } } @@ -1279,12 +1279,12 @@ void si_emit_buffered_gfx_sh_regs_for_mesh(struct si_context *sctx) { if (sctx->gfx_level >= GFX12) { radeon_begin(&sctx->gfx_cs); - gfx12_emit_buffered_sh_regs_inline(&sctx->num_buffered_gfx_sh_regs, - sctx->gfx12.buffered_gfx_sh_regs); + gfx12_emit_buffered_sh_regs_inline(&sctx->buffered_gfx_sh_regs.num, + sctx->buffered_gfx_sh_regs.gfx12.regs); radeon_end(); } else { - gfx11_emit_buffered_sh_regs_inline(sctx, &sctx->num_buffered_gfx_sh_regs, - sctx->gfx11.buffered_gfx_sh_regs); + gfx11_emit_buffered_sh_regs_inline(sctx, &sctx->buffered_gfx_sh_regs.num, + sctx->buffered_gfx_sh_regs.gfx11.regs); } } @@ -1437,12 +1437,12 @@ static void si_emit_draw_packets(struct si_context *sctx, const struct pipe_draw assert(indirect_va % 8 == 0); if (GFX_VERSION >= GFX12) { - gfx12_emit_buffered_sh_regs_inline(&sctx->num_buffered_gfx_sh_regs, - sctx->gfx12.buffered_gfx_sh_regs); + gfx12_emit_buffered_sh_regs_inline(&sctx->buffered_gfx_sh_regs.num, + sctx->buffered_gfx_sh_regs.gfx12.regs); } else if (HAS_SH_PAIRS_PACKED) { radeon_end(); - gfx11_emit_buffered_sh_regs_inline(sctx, &sctx->num_buffered_gfx_sh_regs, - sctx->gfx11.buffered_gfx_sh_regs); + gfx11_emit_buffered_sh_regs_inline(sctx, &sctx->buffered_gfx_sh_regs.num, + sctx->buffered_gfx_sh_regs.gfx11.regs); radeon_begin_again(cs); } @@ -1565,12 +1565,12 @@ static void si_emit_draw_packets(struct si_context *sctx, const struct pipe_draw } if (GFX_VERSION >= GFX12) { - gfx12_emit_buffered_sh_regs_inline(&sctx->num_buffered_gfx_sh_regs, - sctx->gfx12.buffered_gfx_sh_regs); + gfx12_emit_buffered_sh_regs_inline(&sctx->buffered_gfx_sh_regs.num, + sctx->buffered_gfx_sh_regs.gfx12.regs); } else if (HAS_SH_PAIRS_PACKED) { radeon_end(); - gfx11_emit_buffered_sh_regs_inline(sctx, &sctx->num_buffered_gfx_sh_regs, - sctx->gfx11.buffered_gfx_sh_regs); + gfx11_emit_buffered_sh_regs_inline(sctx, &sctx->buffered_gfx_sh_regs.num, + sctx->buffered_gfx_sh_regs.gfx11.regs); radeon_begin_again(cs); }