From bd98df5d8ece369b5a82100cd0206338c889c3b5 Mon Sep 17 00:00:00 2001 From: Francisco Jerez Date: Mon, 21 Feb 2022 21:42:05 -0800 Subject: [PATCH] intel/compiler: Make MAX_VGRF_SIZE macro depend on devinfo and update it for Xe2. Reviewed-by: Jordan Justen Part-of: --- src/intel/compiler/brw_fs.cpp | 4 ++-- src/intel/compiler/brw_fs_reg_allocate.cpp | 2 +- src/intel/compiler/brw_fs_register_coalesce.cpp | 17 +++++++++++------ src/intel/compiler/brw_ir.h | 2 +- src/intel/compiler/brw_vec4_reg_allocate.cpp | 4 ++-- 5 files changed, 17 insertions(+), 12 deletions(-) diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp index f7507daec6e..385b4bfa7be 100644 --- a/src/intel/compiler/brw_fs.cpp +++ b/src/intel/compiler/brw_fs.cpp @@ -2320,7 +2320,7 @@ fs_visitor::split_virtual_grfs() if (split_points[reg]) { has_splits = true; vgrf_has_split[i] = true; - assert(offset <= MAX_VGRF_SIZE); + assert(offset <= MAX_VGRF_SIZE(devinfo)); unsigned grf = alloc.allocate(offset); for (unsigned k = reg - offset; k < reg; k++) new_virtual_grf[k] = grf; @@ -2332,7 +2332,7 @@ fs_visitor::split_virtual_grfs() } /* The last one gets the original register number */ - assert(offset <= MAX_VGRF_SIZE); + assert(offset <= MAX_VGRF_SIZE(devinfo)); alloc.sizes[i] = offset; for (unsigned k = reg - offset; k < reg; k++) new_virtual_grf[k] = i; diff --git a/src/intel/compiler/brw_fs_reg_allocate.cpp b/src/intel/compiler/brw_fs_reg_allocate.cpp index 95060d3eb5c..7166510f0da 100644 --- a/src/intel/compiler/brw_fs_reg_allocate.cpp +++ b/src/intel/compiler/brw_fs_reg_allocate.cpp @@ -116,7 +116,7 @@ brw_alloc_reg_set(struct brw_compiler *compiler, int dispatch_width) * texturing. */ int class_sizes[REG_CLASS_COUNT]; - assert(REG_CLASS_COUNT == MAX_VGRF_SIZE); + assert(REG_CLASS_COUNT == MAX_VGRF_SIZE(devinfo)); for (unsigned i = 0; i < REG_CLASS_COUNT; i++) class_sizes[i] = i + 1; diff --git a/src/intel/compiler/brw_fs_register_coalesce.cpp b/src/intel/compiler/brw_fs_register_coalesce.cpp index 24aa25c94e6..4c9bb3edba8 100644 --- a/src/intel/compiler/brw_fs_register_coalesce.cpp +++ b/src/intel/compiler/brw_fs_register_coalesce.cpp @@ -196,10 +196,10 @@ fs_visitor::register_coalesce() int src_size = 0; int channels_remaining = 0; unsigned src_reg = ~0u, dst_reg = ~0u; - int dst_reg_offset[MAX_VGRF_SIZE]; - fs_inst *mov[MAX_VGRF_SIZE]; - int dst_var[MAX_VGRF_SIZE]; - int src_var[MAX_VGRF_SIZE]; + int *dst_reg_offset = new int[MAX_VGRF_SIZE(devinfo)]; + fs_inst **mov = new fs_inst *[MAX_VGRF_SIZE(devinfo)]; + int *dst_var = new int[MAX_VGRF_SIZE(devinfo)]; + int *src_var = new int[MAX_VGRF_SIZE(devinfo)]; foreach_block_and_inst(block, fs_inst, inst, cfg) { if (!is_coalesce_candidate(this, inst)) @@ -215,10 +215,10 @@ fs_visitor::register_coalesce() src_reg = inst->src[0].nr; src_size = alloc.sizes[inst->src[0].nr]; - assert(src_size <= MAX_VGRF_SIZE); + assert(src_size <= MAX_VGRF_SIZE(devinfo)); channels_remaining = src_size; - memset(mov, 0, sizeof(mov)); + memset(mov, 0, sizeof(*mov) * MAX_VGRF_SIZE(devinfo)); dst_reg = inst->dst.nr; } @@ -340,5 +340,10 @@ fs_visitor::register_coalesce() invalidate_analysis(DEPENDENCY_INSTRUCTIONS); } + delete[] src_var; + delete[] dst_var; + delete[] mov; + delete[] dst_reg_offset; + return progress; } diff --git a/src/intel/compiler/brw_ir.h b/src/intel/compiler/brw_ir.h index d792d6ada24..a123a03ba49 100644 --- a/src/intel/compiler/brw_ir.h +++ b/src/intel/compiler/brw_ir.h @@ -35,7 +35,7 @@ * SIMD32, each component takes up 4 GRFs, so we need to allow up to size-20 * VGRFs to hold the result. */ -#define MAX_VGRF_SIZE 20 +#define MAX_VGRF_SIZE(devinfo) ((devinfo)->ver >= 20 ? 40 : 20) #ifdef __cplusplus struct backend_reg : private brw_reg diff --git a/src/intel/compiler/brw_vec4_reg_allocate.cpp b/src/intel/compiler/brw_vec4_reg_allocate.cpp index c30c68542da..8ba1e80b9a5 100644 --- a/src/intel/compiler/brw_vec4_reg_allocate.cpp +++ b/src/intel/compiler/brw_vec4_reg_allocate.cpp @@ -102,7 +102,7 @@ brw_vec4_alloc_reg_set(struct brw_compiler *compiler) * SEND-from-GRF sources cannot be split, so we also need classes for each * potential message length. */ - assert(REG_CLASS_COUNT == MAX_VGRF_SIZE); + assert(REG_CLASS_COUNT == MAX_VGRF_SIZE(compiler->devinfo)); int class_sizes[REG_CLASS_COUNT]; for (int i = 0; i < REG_CLASS_COUNT; i++) @@ -178,7 +178,7 @@ vec4_visitor::reg_allocate() for (unsigned i = 0; i < alloc.count; i++) { int size = this->alloc.sizes[i]; - assert(size >= 1 && size <= MAX_VGRF_SIZE); + assert(size >= 1 && size <= MAX_VGRF_SIZE(devinfo)); ra_set_node_class(g, i, compiler->vec4_reg_set.classes[size - 1]); for (unsigned j = 0; j < i; j++) {