From bd2c11dfa80b9a750cb3693837f335b480aedb92 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marcin=20=C5=9Alusarz?= Date: Fri, 16 Jul 2021 15:03:20 +0200 Subject: [PATCH] intel/compiler: Load draw_id from XP0 in Task/Mesh shaders MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Marcin Ślusarz Reviewed-by: Lionel Landwerlin Part-of: --- src/intel/compiler/brw_compiler.h | 9 +++++++++ src/intel/compiler/brw_fs_nir.cpp | 10 +++++++++- src/intel/compiler/brw_mesh.cpp | 11 +++++++++++ 3 files changed, 29 insertions(+), 1 deletion(-) diff --git a/src/intel/compiler/brw_compiler.h b/src/intel/compiler/brw_compiler.h index 12700a63b2c..96c1df49d87 100644 --- a/src/intel/compiler/brw_compiler.h +++ b/src/intel/compiler/brw_compiler.h @@ -147,6 +147,12 @@ brw_shader_stage_is_bindless(gl_shader_stage stage) stage <= MESA_SHADER_CALLABLE; } +static inline bool +brw_shader_stage_is_mesh(gl_shader_stage stage) +{ + return stage == MESA_SHADER_TASK || stage == MESA_SHADER_MESH; +} + /** * Program key structures. * @@ -1459,6 +1465,7 @@ struct brw_mue_map { struct brw_task_prog_data { struct brw_cs_prog_data base; struct brw_tue_map map; + bool uses_drawid; }; enum brw_mesh_index_format { @@ -1472,6 +1479,8 @@ struct brw_mesh_prog_data { uint16_t primitive_type; enum brw_mesh_index_format index_format; + + bool uses_drawid; }; /* brw_any_prog_data is prog_data for any stage that maps to an API stage */ diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index 5b17721db9a..2d3b81a2363 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++ b/src/intel/compiler/brw_fs_nir.cpp @@ -155,8 +155,16 @@ emit_system_values_block(nir_block *block, fs_visitor *v) case nir_intrinsic_load_first_vertex: case nir_intrinsic_load_instance_id: case nir_intrinsic_load_base_instance: - case nir_intrinsic_load_draw_id: unreachable("should be lowered by brw_nir_lower_vs_inputs()."); + break; + + case nir_intrinsic_load_draw_id: + /* For Task/Mesh, draw_id will be handled later in + * nir_emit_mesh_task_intrinsic(). + */ + if (!brw_shader_stage_is_mesh(v->stage)) + unreachable("should be lowered by brw_nir_lower_vs_inputs()."); + break; case nir_intrinsic_load_invocation_id: if (v->stage == MESA_SHADER_TESS_CTRL) diff --git a/src/intel/compiler/brw_mesh.cpp b/src/intel/compiler/brw_mesh.cpp index b1b79dcc040..fa24e54d97c 100644 --- a/src/intel/compiler/brw_mesh.cpp +++ b/src/intel/compiler/brw_mesh.cpp @@ -162,6 +162,9 @@ brw_compile_task(const struct brw_compiler *compiler, prog_data->base.local_size[1] = nir->info.workgroup_size[1]; prog_data->base.local_size[2] = nir->info.workgroup_size[2]; + prog_data->uses_drawid = + BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_DRAW_ID); + brw_compute_tue_map(nir, &prog_data->map); const unsigned required_dispatch_width = @@ -533,6 +536,9 @@ brw_compile_mesh(const struct brw_compiler *compiler, /* TODO(mesh): Use other index formats (that are more compact) for optimization. */ prog_data->index_format = BRW_INDEX_FORMAT_U32; + prog_data->uses_drawid = + BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_DRAW_ID); + brw_compute_mue_map(nir, &prog_data->map); const unsigned required_dispatch_width = @@ -980,6 +986,11 @@ fs_visitor::nir_emit_task_mesh_intrinsic(const fs_builder &bld, bld.MOV(dest, retype(brw_vec1_grf(payload.num_regs - 1, 0), dest.type)); break; + case nir_intrinsic_load_draw_id: + /* DrawID comes from Extended Parameter 0 (XP0). */ + bld.MOV(dest, brw_vec1_grf(0, 3)); + break; + case nir_intrinsic_load_local_invocation_index: case nir_intrinsic_load_local_invocation_id: /* Local_ID.X is given by the HW in the shader payload. */