From bc1f438f2aff1d4c4dd3b7fe819e690c4396ac7c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Wed, 8 Oct 2025 18:13:15 +0200 Subject: [PATCH] radv: Remove qf argument from radv_cs_emit_write_event_eop Part-of: --- src/amd/vulkan/radv_cmd_buffer.c | 19 +++++++++---------- src/amd/vulkan/radv_cs.c | 18 +++++++++--------- src/amd/vulkan/radv_cs.h | 6 +++--- src/amd/vulkan/radv_perfcounter.c | 4 ++-- src/amd/vulkan/radv_query.c | 12 ++++++------ src/amd/vulkan/radv_queue.c | 4 ++-- 6 files changed, 31 insertions(+), 32 deletions(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 0696a863375..7d2e4aa85f8 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -1514,8 +1514,8 @@ radv_gang_follower_sem_dirty(const struct radv_cmd_buffer *cmd_buffer) } ALWAYS_INLINE static bool -radv_flush_gang_semaphore(struct radv_cmd_buffer *cmd_buffer, struct radv_cmd_stream *cs, - const enum radv_queue_family qf, const uint32_t va_off, const uint32_t value) +radv_flush_gang_semaphore(struct radv_cmd_buffer *cmd_buffer, struct radv_cmd_stream *cs, const uint32_t va_off, + const uint32_t value) { struct radv_device *device = radv_cmd_buffer_device(cmd_buffer); const struct radv_physical_device *pdev = radv_device_physical(device); @@ -1525,7 +1525,7 @@ radv_flush_gang_semaphore(struct radv_cmd_buffer *cmd_buffer, struct radv_cmd_st ASSERTED unsigned cdw_max = radeon_check_space(device->ws, cs->b, 12); - radv_cs_emit_write_event_eop(cs, pdev->info.gfx_level, qf, V_028A90_BOTTOM_OF_PIPE_TS, 0, EOP_DST_SEL_MEM, + radv_cs_emit_write_event_eop(cs, pdev->info.gfx_level, V_028A90_BOTTOM_OF_PIPE_TS, 0, EOP_DST_SEL_MEM, EOP_DATA_SEL_VALUE_32BIT, cmd_buffer->gang.sem.va + va_off, value, cmd_buffer->gfx9_eop_bug_va); @@ -1541,7 +1541,7 @@ radv_flush_gang_leader_semaphore(struct radv_cmd_buffer *cmd_buffer) /* Gang leader writes a value to the semaphore which the follower can wait for. */ cmd_buffer->gang.sem.emitted_leader_value = cmd_buffer->gang.sem.leader_value; - return radv_flush_gang_semaphore(cmd_buffer, cmd_buffer->cs, cmd_buffer->qf, 0, cmd_buffer->gang.sem.leader_value); + return radv_flush_gang_semaphore(cmd_buffer, cmd_buffer->cs, 0, cmd_buffer->gang.sem.leader_value); } ALWAYS_INLINE static bool @@ -1552,8 +1552,7 @@ radv_flush_gang_follower_semaphore(struct radv_cmd_buffer *cmd_buffer) /* Follower writes a value to the semaphore which the gang leader can wait for. */ cmd_buffer->gang.sem.emitted_follower_value = cmd_buffer->gang.sem.follower_value; - return radv_flush_gang_semaphore(cmd_buffer, cmd_buffer->gang.cs, RADV_QUEUE_COMPUTE, 4, - cmd_buffer->gang.sem.follower_value); + return radv_flush_gang_semaphore(cmd_buffer, cmd_buffer->gang.cs, 4, cmd_buffer->gang.sem.follower_value); } ALWAYS_INLINE static void @@ -14485,8 +14484,8 @@ write_event(struct radv_cmd_buffer *cmd_buffer, struct radv_event *event, VkPipe event_type = V_028A90_BOTTOM_OF_PIPE_TS; } - radv_cs_emit_write_event_eop(cs, pdev->info.gfx_level, cmd_buffer->qf, event_type, 0, EOP_DST_SEL_MEM, - EOP_DATA_SEL_VALUE_32BIT, va, value, cmd_buffer->gfx9_eop_bug_va); + radv_cs_emit_write_event_eop(cs, pdev->info.gfx_level, event_type, 0, EOP_DST_SEL_MEM, EOP_DATA_SEL_VALUE_32BIT, + va, value, cmd_buffer->gfx9_eop_bug_va); } assert(cs->b->cdw <= cdw_max); @@ -15189,8 +15188,8 @@ radv_CmdWriteBufferMarker2AMD(VkCommandBuffer commandBuffer, VkPipelineStageFlag radeon_emit(va >> 32); radeon_end(); } else { - radv_cs_emit_write_event_eop(cs, pdev->info.gfx_level, cmd_buffer->qf, V_028A90_BOTTOM_OF_PIPE_TS, 0, - EOP_DST_SEL_MEM, EOP_DATA_SEL_VALUE_32BIT, va, marker, cmd_buffer->gfx9_eop_bug_va); + radv_cs_emit_write_event_eop(cs, pdev->info.gfx_level, V_028A90_BOTTOM_OF_PIPE_TS, 0, EOP_DST_SEL_MEM, + EOP_DATA_SEL_VALUE_32BIT, va, marker, cmd_buffer->gfx9_eop_bug_va); } assert(cs->b->cdw <= cdw_max); diff --git a/src/amd/vulkan/radv_cs.c b/src/amd/vulkan/radv_cs.c index c6759db1a0e..1b3a91859af 100644 --- a/src/amd/vulkan/radv_cs.c +++ b/src/amd/vulkan/radv_cs.c @@ -17,11 +17,11 @@ #include "sid.h" void -radv_cs_emit_write_event_eop(struct radv_cmd_stream *cs, enum amd_gfx_level gfx_level, enum radv_queue_family qf, - unsigned event, unsigned event_flags, unsigned dst_sel, unsigned data_sel, uint64_t va, - uint32_t new_fence, uint64_t gfx9_eop_bug_va) +radv_cs_emit_write_event_eop(struct radv_cmd_stream *cs, enum amd_gfx_level gfx_level, unsigned event, + unsigned event_flags, unsigned dst_sel, unsigned data_sel, uint64_t va, uint32_t new_fence, + uint64_t gfx9_eop_bug_va) { - if (qf == RADV_QUEUE_TRANSFER) { + if (cs->hw_ip == AMD_IP_SDMA) { radv_sdma_emit_fence(cs, va, new_fence); return; } @@ -30,7 +30,7 @@ radv_cs_emit_write_event_eop(struct radv_cmd_stream *cs, enum amd_gfx_level gfx_ if (gfx_level == GFX7 && (event == V_028A90_CS_DONE || event == V_028A90_PS_DONE)) event = V_028A90_BOTTOM_OF_PIPE_TS; - const bool is_mec = qf == RADV_QUEUE_COMPUTE && gfx_level >= GFX7; + const bool is_mec = cs->hw_ip == AMD_IP_COMPUTE && gfx_level >= GFX7; unsigned op = EVENT_TYPE(event) | EVENT_INDEX(event == V_028A90_CS_DONE || event == V_028A90_PS_DONE ? 6 : 5) | event_flags; unsigned sel = EOP_DST_SEL(dst_sel) | EOP_DATA_SEL(data_sel); @@ -315,7 +315,7 @@ gfx10_cs_emit_cache_flush(struct radv_cmd_stream *cs, enum amd_gfx_level gfx_lev assert(flush_cnt); (*flush_cnt)++; - radv_cs_emit_write_event_eop(cs, gfx_level, qf, cb_db_event, + radv_cs_emit_write_event_eop(cs, gfx_level, cb_db_event, S_490_GLM_WB(glm_wb) | S_490_GLM_INV(glm_inv) | S_490_GLV_INV(glv_inv) | S_490_GL1_INV(gl1_inv) | S_490_GL2_INV(gl2_inv) | S_490_GL2_WB(gl2_wb) | S_490_SEQ(gcr_seq), @@ -410,7 +410,7 @@ radv_cs_emit_cache_flush(struct radeon_winsys *ws, struct radv_cmd_stream *cs, e /* Necessary for DCC */ if (gfx_level >= GFX8) { - radv_cs_emit_write_event_eop(cs, gfx_level, qf, V_028A90_FLUSH_AND_INV_CB_DATA_TS, 0, EOP_DST_SEL_MEM, + radv_cs_emit_write_event_eop(cs, gfx_level, V_028A90_FLUSH_AND_INV_CB_DATA_TS, 0, EOP_DST_SEL_MEM, EOP_DATA_SEL_DISCARD, 0, 0, gfx9_eop_bug_va); } @@ -497,8 +497,8 @@ radv_cs_emit_cache_flush(struct radeon_winsys *ws, struct radv_cmd_stream *cs, e assert(flush_cnt); (*flush_cnt)++; - radv_cs_emit_write_event_eop(cs, gfx_level, qf, cb_db_event, tc_flags, EOP_DST_SEL_MEM, - EOP_DATA_SEL_VALUE_32BIT, flush_va, *flush_cnt, gfx9_eop_bug_va); + radv_cs_emit_write_event_eop(cs, gfx_level, cb_db_event, tc_flags, EOP_DST_SEL_MEM, EOP_DATA_SEL_VALUE_32BIT, + flush_va, *flush_cnt, gfx9_eop_bug_va); radv_cp_wait_mem(cs, qf, WAIT_REG_MEM_EQUAL, flush_va, *flush_cnt, 0xffffffff); } diff --git a/src/amd/vulkan/radv_cs.h b/src/amd/vulkan/radv_cs.h index eb1983e74a4..85fcfd52dfa 100644 --- a/src/amd/vulkan/radv_cs.h +++ b/src/amd/vulkan/radv_cs.h @@ -396,9 +396,9 @@ radv_cs_write_data(const struct radv_device *device, struct radv_cmd_stream *cs, assert(cs->b->cdw == cdw_end); } -void radv_cs_emit_write_event_eop(struct radv_cmd_stream *cs, enum amd_gfx_level gfx_level, enum radv_queue_family qf, - unsigned event, unsigned event_flags, unsigned dst_sel, unsigned data_sel, - uint64_t va, uint32_t new_fence, uint64_t gfx9_eop_bug_va); +void radv_cs_emit_write_event_eop(struct radv_cmd_stream *cs, enum amd_gfx_level gfx_level, unsigned event, + unsigned event_flags, unsigned dst_sel, unsigned data_sel, uint64_t va, + uint32_t new_fence, uint64_t gfx9_eop_bug_va); void radv_cs_emit_cache_flush(struct radeon_winsys *ws, struct radv_cmd_stream *cs, enum amd_gfx_level gfx_level, uint32_t *flush_cnt, uint64_t flush_va, enum radv_queue_family qf, diff --git a/src/amd/vulkan/radv_perfcounter.c b/src/amd/vulkan/radv_perfcounter.c index d89229d4b23..e0d29ffa87d 100644 --- a/src/amd/vulkan/radv_perfcounter.c +++ b/src/amd/vulkan/radv_perfcounter.c @@ -764,8 +764,8 @@ radv_pc_end_query(struct radv_cmd_buffer *cmd_buffer, struct radv_pc_query_pool radv_cs_add_buffer(device->ws, cs->b, device->perf_counter_bo); uint64_t perf_ctr_va = radv_buffer_get_va(device->perf_counter_bo) + PERF_CTR_BO_FENCE_OFFSET; - radv_cs_emit_write_event_eop(cs, pdev->info.gfx_level, cmd_buffer->qf, V_028A90_BOTTOM_OF_PIPE_TS, 0, - EOP_DST_SEL_MEM, EOP_DATA_SEL_VALUE_32BIT, perf_ctr_va, 1, cmd_buffer->gfx9_fence_va); + radv_cs_emit_write_event_eop(cs, pdev->info.gfx_level, V_028A90_BOTTOM_OF_PIPE_TS, 0, EOP_DST_SEL_MEM, + EOP_DATA_SEL_VALUE_32BIT, perf_ctr_va, 1, cmd_buffer->gfx9_fence_va); radv_cp_wait_mem(cs, cmd_buffer->qf, WAIT_REG_MEM_EQUAL, perf_ctr_va, 1, 0xffffffff); radv_pc_wait_idle(cmd_buffer); diff --git a/src/amd/vulkan/radv_query.c b/src/amd/vulkan/radv_query.c index 5c0c83cb316..71346801f46 100644 --- a/src/amd/vulkan/radv_query.c +++ b/src/amd/vulkan/radv_query.c @@ -769,8 +769,8 @@ radv_end_pipeline_stat_query(struct radv_cmd_buffer *cmd_buffer, struct radv_que } } - radv_cs_emit_write_event_eop(cs, pdev->info.gfx_level, cmd_buffer->qf, V_028A90_BOTTOM_OF_PIPE_TS, 0, - EOP_DST_SEL_MEM, EOP_DATA_SEL_VALUE_32BIT, avail_va, 1, cmd_buffer->gfx9_eop_bug_va); + radv_cs_emit_write_event_eop(cs, pdev->info.gfx_level, V_028A90_BOTTOM_OF_PIPE_TS, 0, EOP_DST_SEL_MEM, + EOP_DATA_SEL_VALUE_32BIT, avail_va, 1, cmd_buffer->gfx9_eop_bug_va); } static void @@ -1641,8 +1641,8 @@ radv_end_ms_prim_query(struct radv_cmd_buffer *cmd_buffer, uint64_t va, uint64_t radv_emit_event_write(&pdev->info, cs, RADV_EVENT_WRITE_PIPELINE_STAT, va); - radv_cs_emit_write_event_eop(cs, pdev->info.gfx_level, cmd_buffer->qf, V_028A90_BOTTOM_OF_PIPE_TS, 0, - EOP_DST_SEL_MEM, EOP_DATA_SEL_VALUE_32BIT, avail_va, 1, cmd_buffer->gfx9_eop_bug_va); + radv_cs_emit_write_event_eop(cs, pdev->info.gfx_level, V_028A90_BOTTOM_OF_PIPE_TS, 0, EOP_DST_SEL_MEM, + EOP_DATA_SEL_VALUE_32BIT, avail_va, 1, cmd_buffer->gfx9_eop_bug_va); } else { gfx10_copy_shader_query_gfx(cmd_buffer, true, RADV_SHADER_QUERY_MS_PRIM_GEN_OFFSET, va + 8); radv_cs_write_data_imm(cs, V_370_ME, va + 12, 0x80000000); @@ -2735,8 +2735,8 @@ radv_write_timestamp(struct radv_cmd_buffer *cmd_buffer, uint64_t va, VkPipeline radeon_emit(va >> 32); radeon_end(); } else { - radv_cs_emit_write_event_eop(cs, pdev->info.gfx_level, cmd_buffer->qf, V_028A90_BOTTOM_OF_PIPE_TS, 0, - EOP_DST_SEL_MEM, EOP_DATA_SEL_TIMESTAMP, va, 0, cmd_buffer->gfx9_eop_bug_va); + radv_cs_emit_write_event_eop(cs, pdev->info.gfx_level, V_028A90_BOTTOM_OF_PIPE_TS, 0, EOP_DST_SEL_MEM, + EOP_DATA_SEL_TIMESTAMP, va, 0, cmd_buffer->gfx9_eop_bug_va); } } diff --git a/src/amd/vulkan/radv_queue.c b/src/amd/vulkan/radv_queue.c index 3089b52d624..eb95a7b3d5a 100644 --- a/src/amd/vulkan/radv_queue.c +++ b/src/amd/vulkan/radv_queue.c @@ -1495,8 +1495,8 @@ radv_create_gang_wait_preambles_postambles(struct radv_queue *queue) */ radv_cp_wait_mem(leader_post_cs, queue->state.qf, WAIT_REG_MEM_GREATER_OR_EQUAL, leader_wait_va, 1, 0xffffffff); radv_cs_write_data(device, leader_post_cs, queue->state.qf, V_370_ME, leader_wait_va, 1, &zero, false); - radv_cs_emit_write_event_eop(ace_post_cs, pdev->info.gfx_level, RADV_QUEUE_COMPUTE, V_028A90_BOTTOM_OF_PIPE_TS, 0, - EOP_DST_SEL_MEM, EOP_DATA_SEL_VALUE_32BIT, leader_wait_va, 1, 0); + radv_cs_emit_write_event_eop(ace_post_cs, pdev->info.gfx_level, V_028A90_BOTTOM_OF_PIPE_TS, 0, EOP_DST_SEL_MEM, + EOP_DATA_SEL_VALUE_32BIT, leader_wait_va, 1, 0); r = radv_finalize_cmd_stream(device, leader_pre_cs); if (r != VK_SUCCESS)