diff --git a/src/intel/compiler/brw_compiler.h b/src/intel/compiler/brw_compiler.h
index ecaa8d7f31b..91c624302c4 100644
--- a/src/intel/compiler/brw_compiler.h
+++ b/src/intel/compiler/brw_compiler.h
@@ -607,24 +607,11 @@ struct brw_wm_prog_data {
    unsigned num_per_primitive_inputs;
    unsigned num_varying_inputs;
 
-   uint8_t reg_blocks_8;
-   uint8_t reg_blocks_16;
-   uint8_t reg_blocks_32;
-
    uint8_t dispatch_grf_start_reg_16;
    uint8_t dispatch_grf_start_reg_32;
    uint32_t prog_offset_16;
    uint32_t prog_offset_32;
 
-   struct {
-      /** @{
-       * surface indices the WM-specific surfaces
-       */
-      uint32_t render_target_read_start;
-      /** @} */
-   } binding_table;
-
-   uint8_t color_outputs_written;
    uint8_t computed_depth_mode;
 
    /**
@@ -709,11 +696,6 @@ struct brw_wm_prog_data {
     */
    uint64_t inputs;
 
-   /* Mapping of VUE slots to interpolation modes.
-    * Used by the Gfx4-5 clip/sf/wm stages.
-    */
-   unsigned char interp_mode[65]; /* BRW_VARYING_SLOT_COUNT */
-
    /**
     * Map from gl_varying_slot to the position within the FS setup data
     * payload where the varying's attribute vertex deltas should be delivered.
@@ -839,22 +821,6 @@ _brw_wm_prog_data_dispatch_grf_start_reg(const struct brw_wm_prog_data *prog_dat
    _brw_wm_prog_data_dispatch_grf_start_reg(prog_data, \
       brw_wm_state_simd_width_for_ksp(wm_state, ksp_idx))
 
-static inline uint8_t
-_brw_wm_prog_data_reg_blocks(const struct brw_wm_prog_data *prog_data,
-                             unsigned simd_width)
-{
-   switch (simd_width) {
-   case 8: return prog_data->reg_blocks_8;
-   case 16: return prog_data->reg_blocks_16;
-   case 32: return prog_data->reg_blocks_32;
-   default: return 0;
-   }
-}
-
-#define brw_wm_prog_data_reg_blocks(prog_data, wm_state, ksp_idx) \
-   _brw_wm_prog_data_reg_blocks(prog_data, \
-      brw_wm_state_simd_width_for_ksp(wm_state, ksp_idx))
-
 static inline bool
 brw_wm_prog_data_is_persample(const struct brw_wm_prog_data *prog_data,
                               enum intel_msaa_flags pushed_msaa_flags)
diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index 0eb8513e552..fe194863294 100644
--- a/src/intel/compiler/brw_fs.cpp
+++ b/src/intel/compiler/brw_fs.cpp
@@ -3304,7 +3304,6 @@ brw_nir_populate_wm_prog_data(nir_shader *shader,
                           shader->info.fs.uses_demote;
    prog_data->uses_omask = !key->ignore_sample_mask_out &&
       (shader->info.outputs_written & BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK));
-   prog_data->color_outputs_written = key->color_outputs_valid;
    prog_data->max_polygons = 1;
    prog_data->computed_depth_mode = computed_depth_mode(shader);
    prog_data->computed_stencil =
@@ -3446,17 +3445,6 @@ brw_nir_populate_wm_prog_data(nir_shader *shader,
    brw_compute_flat_inputs(prog_data, shader);
 }
 
-/**
- * Pre-gfx6, the register file of the EUs was shared between threads,
- * and each thread used some subset allocated on a 16-register block
- * granularity.  The unit states wanted these block counts.
- */
-static inline int
-brw_register_blocks(int reg_count)
-{
-   return ALIGN(reg_count, 16) / 16 - 1;
-}
-
 const unsigned *
 brw_compile_fs(const struct brw_compiler *compiler,
                struct brw_compile_fs_params *params)
@@ -3521,7 +3509,6 @@ brw_compile_fs(const struct brw_compiler *compiler,
          assert(v8->payload().num_regs % reg_unit(devinfo) == 0);
          prog_data->base.dispatch_grf_start_reg = v8->payload().num_regs / reg_unit(devinfo);
 
-         prog_data->reg_blocks_8 = brw_register_blocks(v8->grf_used);
          const performance &perf = v8->performance_analysis.require();
          throughput = MAX2(throughput, perf.throughput);
          has_spilled = v8->spilled_any_registers;
@@ -3561,7 +3548,6 @@ brw_compile_fs(const struct brw_compiler *compiler,
          assert(v16->payload().num_regs % reg_unit(devinfo) == 0);
          prog_data->dispatch_grf_start_reg_16 = v16->payload().num_regs / reg_unit(devinfo);
 
-         prog_data->reg_blocks_16 = brw_register_blocks(v16->grf_used);
          const performance &perf = v16->performance_analysis.require();
          throughput = MAX2(throughput, perf.throughput);
          has_spilled = v16->spilled_any_registers;
@@ -3603,7 +3589,6 @@ brw_compile_fs(const struct brw_compiler *compiler,
             assert(v32->payload().num_regs % reg_unit(devinfo) == 0);
             prog_data->dispatch_grf_start_reg_32 = v32->payload().num_regs / reg_unit(devinfo);
 
-            prog_data->reg_blocks_32 = brw_register_blocks(v32->grf_used);
             throughput = MAX2(throughput, perf.throughput);
          }
       }
@@ -3676,8 +3661,6 @@ brw_compile_fs(const struct brw_compiler *compiler,
       if (multi_cfg) {
          assert(vmulti->payload().num_regs % reg_unit(devinfo) == 0);
          prog_data->base.dispatch_grf_start_reg = vmulti->payload().num_regs / reg_unit(devinfo);
-
-         prog_data->reg_blocks_8 = brw_register_blocks(vmulti->grf_used);
       }
    }