From bbab69d3435e380842f2364507f29bdae491420b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Fri, 12 Sep 2025 16:32:59 -0400 Subject: [PATCH] radv: fix load_smem alignment MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit radv_cmd_buffer_upload_alloc_aligned is used with alignment=0, which guarantees that the alignment is at least 4. Fixes: 9e16ed7a134 - ac/nir: switch nir_load_smem_amd uses to ac_nir_load_smem wrapper Reviewed-by: Timur Kristóf Part-of: --- src/amd/vulkan/nir/radv_nir_apply_pipeline_layout.c | 4 ++-- src/amd/vulkan/nir/radv_nir_lower_abi.c | 2 +- src/amd/vulkan/nir/radv_nir_lower_vs_inputs.c | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/amd/vulkan/nir/radv_nir_apply_pipeline_layout.c b/src/amd/vulkan/nir/radv_nir_apply_pipeline_layout.c index a242542641d..fcf9a4592d0 100644 --- a/src/amd/vulkan/nir/radv_nir_apply_pipeline_layout.c +++ b/src/amd/vulkan/nir/radv_nir_apply_pipeline_layout.c @@ -168,7 +168,7 @@ load_buffer_descriptor(nir_builder *b, apply_layout_state *state, nir_def *rsrc, return nir_iadd(b, nir_channel(b, rsrc, 0), nir_channel(b, rsrc, 1)); nir_def *desc_set = convert_pointer_to_64_bit(b, state, nir_channel(b, rsrc, 0)); - return ac_nir_load_smem(b, 4, desc_set, nir_channel(b, rsrc, 1), 16, 0); + return ac_nir_load_smem(b, 4, desc_set, nir_channel(b, rsrc, 1), 4, 0); } static void @@ -186,7 +186,7 @@ visit_get_ssbo_size(nir_builder *b, apply_layout_state *state, nir_intrinsic_ins } else { /* load the entire descriptor so it can be CSE'd */ nir_def *ptr = convert_pointer_to_64_bit(b, state, nir_channel(b, rsrc, 0)); - nir_def *desc = ac_nir_load_smem(b, 4, ptr, nir_channel(b, rsrc, 1), 16, 0); + nir_def *desc = ac_nir_load_smem(b, 4, ptr, nir_channel(b, rsrc, 1), 4, 0); size = nir_channel(b, desc, 2); } diff --git a/src/amd/vulkan/nir/radv_nir_lower_abi.c b/src/amd/vulkan/nir/radv_nir_lower_abi.c index 68f1d2cce58..88b4dd67d6f 100644 --- a/src/amd/vulkan/nir/radv_nir_lower_abi.c +++ b/src/amd/vulkan/nir/radv_nir_lower_abi.c @@ -367,7 +367,7 @@ lower_abi_instr(nir_builder *b, nir_intrinsic_instr *intrin, void *state) nir_def *ptr = nir_pack_64_2x32_split(b, ac_nir_load_arg(b, &s->args->ac, s->args->streamout_buffers), nir_imm_int(b, s->address32_hi)); replacement = - ac_nir_load_smem(b, 4, ptr, nir_imm_int(b, nir_intrinsic_base(intrin) * 16), 16, ACCESS_CAN_SPECULATE); + ac_nir_load_smem(b, 4, ptr, nir_imm_int(b, nir_intrinsic_base(intrin) * 16), 4, ACCESS_CAN_SPECULATE); break; } case nir_intrinsic_load_xfb_state_address_gfx12_amd: diff --git a/src/amd/vulkan/nir/radv_nir_lower_vs_inputs.c b/src/amd/vulkan/nir/radv_nir_lower_vs_inputs.c index 998d90cd721..a2f3ec8f7fe 100644 --- a/src/amd/vulkan/nir/radv_nir_lower_vs_inputs.c +++ b/src/amd/vulkan/nir/radv_nir_lower_vs_inputs.c @@ -235,7 +235,7 @@ lower_load_vs_input(nir_builder *b, nir_intrinsic_instr *intrin, lower_vs_inputs nir_def *vertex_buffers_arg = ac_nir_load_arg(b, &s->args->ac, s->args->ac.vertex_buffers); nir_def *vertex_buffers = nir_pack_64_2x32_split(b, vertex_buffers_arg, nir_imm_int(b, s->gpu_info->address32_hi)); nir_def *descriptor = - ac_nir_load_smem(b, 4, vertex_buffers, nir_imm_int(b, desc_index * 16), 16, ACCESS_CAN_SPECULATE); + ac_nir_load_smem(b, 4, vertex_buffers, nir_imm_int(b, desc_index * 16), 4, ACCESS_CAN_SPECULATE); nir_def *base_index = calc_vs_input_index(b, location, s); nir_def *zero = nir_imm_int(b, 0);