diff --git a/src/asahi/compiler/agx_compile.c b/src/asahi/compiler/agx_compile.c
index 3179b6d2d2e..64fd8e3d7af 100644
--- a/src/asahi/compiler/agx_compile.c
+++ b/src/asahi/compiler/agx_compile.c
@@ -2634,13 +2634,9 @@ struct interp_masks {
 };
 
 static bool
-agx_gather_interp(nir_builder *b, nir_instr *instr, void *data)
+agx_gather_interp(nir_builder *b, nir_intrinsic_instr *intr, void *data)
 {
    struct interp_masks *masks = data;
-   if (instr->type != nir_instr_type_intrinsic)
-      return false;
-
-   nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
 
    if (intr->intrinsic == nir_intrinsic_load_input) {
       nir_io_semantics sem = nir_intrinsic_io_semantics(intr);
@@ -2666,9 +2662,7 @@ agx_interp_masks(nir_shader *nir)
    assert(nir->info.stage == MESA_SHADER_FRAGMENT);
 
    struct interp_masks masks = {0};
-   nir_shader_instructions_pass(nir, agx_gather_interp, nir_metadata_all,
-                                &masks);
-
+   nir_shader_intrinsics_pass(nir, agx_gather_interp, nir_metadata_all, &masks);
    return masks;
 }
 
diff --git a/src/asahi/compiler/agx_nir_lower_load_mask.c b/src/asahi/compiler/agx_nir_lower_load_mask.c
index ec858e8f103..43d0ee69137 100644
--- a/src/asahi/compiler/agx_nir_lower_load_mask.c
+++ b/src/asahi/compiler/agx_nir_lower_load_mask.c
@@ -12,12 +12,8 @@
  * load_interpolated_input becomes iter instructions, which lack a write mask.
  */
 static bool
-pass(struct nir_builder *b, nir_instr *instr, UNUSED void *data)
+pass(struct nir_builder *b, nir_intrinsic_instr *intr, UNUSED void *data)
 {
-   if (instr->type != nir_instr_type_intrinsic)
-      return false;
-
-   nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
    if (intr->intrinsic != nir_intrinsic_load_interpolated_input)
       return false;
 
@@ -25,7 +21,7 @@ pass(struct nir_builder *b, nir_instr *instr, UNUSED void *data)
    if (mask == 0 || mask == nir_component_mask(intr->num_components))
       return false;
 
-   b->cursor = nir_before_instr(instr);
+   b->cursor = nir_before_instr(&intr->instr);
    unsigned bit_size = intr->def.bit_size;
    nir_def *comps[4] = {NULL};
 
@@ -39,7 +35,7 @@ pass(struct nir_builder *b, nir_instr *instr, UNUSED void *data)
          assert(next_zero >= 2);
          assert(count >= 1);
 
-         nir_instr *clone = nir_instr_clone(b->shader, instr);
+         nir_instr *clone = nir_instr_clone(b->shader, &intr->instr);
          nir_intrinsic_instr *clone_intr = nir_instr_as_intrinsic(clone);
 
          /* Shrink the load to count contiguous components */
@@ -75,6 +71,6 @@ pass(struct nir_builder *b, nir_instr *instr, UNUSED void *data)
 bool
 agx_nir_lower_load_mask(nir_shader *shader)
 {
-   return nir_shader_instructions_pass(
+   return nir_shader_intrinsics_pass(
       shader, pass, nir_metadata_block_index | nir_metadata_dominance, NULL);
 }
diff --git a/src/asahi/lib/agx_nir_lower_msaa.c b/src/asahi/lib/agx_nir_lower_msaa.c
index 78db4e04085..43da2bea14f 100644
--- a/src/asahi/lib/agx_nir_lower_msaa.c
+++ b/src/asahi/lib/agx_nir_lower_msaa.c
@@ -9,20 +9,16 @@
 #include "nir_builder.h"
 
 static bool
-lower_wrapped(nir_builder *b, nir_instr *instr, void *data)
+lower_wrapped(nir_builder *b, nir_intrinsic_instr *intr, void *data)
 {
    nir_def *sample_id = data;
-   if (instr->type != nir_instr_type_intrinsic)
-      return false;
-
-   nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
-   b->cursor = nir_before_instr(instr);
+   b->cursor = nir_before_instr(&intr->instr);
 
    switch (intr->intrinsic) {
    case nir_intrinsic_load_sample_id: {
       unsigned size = intr->def.bit_size;
       nir_def_rewrite_uses(&intr->def, nir_u2uN(b, sample_id, size));
-      nir_instr_remove(instr);
+      nir_instr_remove(&intr->instr);
       return true;
    }
 
@@ -90,21 +86,18 @@ agx_nir_wrap_per_sample_loop(nir_shader *shader, uint8_t nr_samples)
    nir_metadata_preserve(impl, nir_metadata_none);
 
    /* Use the loop counter as the sample ID each iteration */
-   nir_shader_instructions_pass(
-      shader, lower_wrapped, nir_metadata_block_index | nir_metadata_dominance,
-      index);
+   nir_shader_intrinsics_pass(shader, lower_wrapped,
+                              nir_metadata_block_index | nir_metadata_dominance,
+                              index);
    return true;
 }
 
 static bool
-lower_sample_mask_write(nir_builder *b, nir_instr *instr, void *data)
+lower_sample_mask_write(nir_builder *b, nir_intrinsic_instr *intr, void *data)
 {
    struct agx_msaa_state *state = data;
-   if (instr->type != nir_instr_type_intrinsic)
-      return false;
+   b->cursor = nir_before_instr(&intr->instr);
 
-   nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
-   b->cursor = nir_before_instr(instr);
    if (intr->intrinsic != nir_intrinsic_store_output)
       return false;
 
@@ -112,13 +105,8 @@ lower_sample_mask_write(nir_builder *b, nir_instr *instr, void *data)
    if (sem.location != FRAG_RESULT_SAMPLE_MASK)
       return false;
 
-   /* Sample mask writes are ignored unless multisampling is used. */
-   if (state->nr_samples == 1) {
-      nir_instr_remove(instr);
-      return true;
-   }
-
-   /* The Vulkan spec says:
+   /* Sample mask writes are ignored unless multisampling is used. If it is
+    * used, the Vulkan spec says:
     *
     *    If sample shading is enabled, bits written to SampleMask
     *    corresponding to samples that are not being shaded by the fragment
@@ -127,9 +115,12 @@ lower_sample_mask_write(nir_builder *b, nir_instr *instr, void *data)
     * That will be satisfied by outputting gl_SampleMask for the whole pixel
     * and then lowering sample shading after (splitting up discard targets).
     */
-   nir_discard_agx(b, nir_inot(b, nir_u2u16(b, intr->src[0].ssa)));
-   b->shader->info.fs.uses_discard = true;
-   nir_instr_remove(instr);
+   if (state->nr_samples != 1) {
+      nir_discard_agx(b, nir_inot(b, nir_u2u16(b, intr->src[0].ssa)));
+      b->shader->info.fs.uses_discard = true;
+   }
+
+   nir_instr_remove(&intr->instr);
    return true;
 }
 
@@ -182,7 +173,7 @@ agx_nir_lower_monolithic_msaa(nir_shader *shader, struct agx_msaa_state *state)
 
    /* Lower gl_SampleMask writes */
    if (shader->info.outputs_written & BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK)) {
-      nir_shader_instructions_pass(
+      nir_shader_intrinsics_pass(
          shader, lower_sample_mask_write,
          nir_metadata_block_index | nir_metadata_dominance, state);
    }
diff --git a/src/asahi/lib/agx_nir_lower_vbo.c b/src/asahi/lib/agx_nir_lower_vbo.c
index 97c3e2fec57..420e88a509d 100644
--- a/src/asahi/lib/agx_nir_lower_vbo.c
+++ b/src/asahi/lib/agx_nir_lower_vbo.c
@@ -104,17 +104,13 @@ apply_swizzle_channel(nir_builder *b, nir_def *vec, unsigned swizzle,
 }
 
 static bool
-pass(struct nir_builder *b, nir_instr *instr, void *data)
+pass(struct nir_builder *b, nir_intrinsic_instr *intr, void *data)
 {
-   if (instr->type != nir_instr_type_intrinsic)
-      return false;
-
-   nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
    if (intr->intrinsic != nir_intrinsic_load_input)
       return false;
 
    struct agx_attribute *attribs = data;
-   b->cursor = nir_before_instr(instr);
+   b->cursor = nir_before_instr(&intr->instr);
 
    nir_src *offset_src = nir_get_io_offset_src(intr);
    assert(nir_src_is_const(*offset_src) && "no attribute indirects");
@@ -293,6 +289,6 @@ bool
 agx_nir_lower_vbo(nir_shader *shader, struct agx_attribute *attribs)
 {
    assert(shader->info.stage == MESA_SHADER_VERTEX);
-   return nir_shader_instructions_pass(
+   return nir_shader_intrinsics_pass(
       shader, pass, nir_metadata_block_index | nir_metadata_dominance, attribs);
 }