diff --git a/src/amd/vulkan/radv_queue.c b/src/amd/vulkan/radv_queue.c
index b8257af05ad..dd0cf8701c7 100644
--- a/src/amd/vulkan/radv_queue.c
+++ b/src/amd/vulkan/radv_queue.c
@@ -701,7 +701,7 @@ radv_emit_ge_rings(struct radv_device *device, struct radeon_cmdbuf *cs, struct
                   S_0309AC_PAB_TEMPORAL(gfx12_load_last_use_discard) | S_0309AC_SPEC_DATA_READ(gfx12_spec_read_auto) |
                   S_0309AC_FORCE_SE_SCOPE(1) | S_0309AC_PAB_NOFILL(1)); /* R_0309AC_GE_PRIM_RING_SIZE */
 
-      if (pdev->info.gfx_level == GFX12) {
+      if (pdev->info.gfx_level == GFX12 && pdev->info.pfp_fw_version >= 2680) {
          /* Mitigate the HiZ GPU hang by increasing a timeout when BOTTOM_OF_PIPE_TS is used as the
           * workaround. This must be emitted when the gfx queue is idle.
           */
diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.cpp b/src/gallium/drivers/radeonsi/si_state_shaders.cpp
index a716cbf5a9c..144ffbda2be 100644
--- a/src/gallium/drivers/radeonsi/si_state_shaders.cpp
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.cpp
@@ -5161,7 +5161,7 @@ static void si_emit_spi_ge_ring_state(struct si_context *sctx, unsigned index)
                      S_0309AC_FORCE_SE_SCOPE(1) |
                      S_0309AC_PAB_NOFILL(1));         /* R_0309AC_GE_PRIM_RING_SIZE */
 
-         if (sctx->gfx_level == GFX12) {
+         if (sctx->gfx_level == GFX12 && sscreen->info.pfp_fw_version >= 2680) {
             /* Mitigate the HiZ GPU hang by increasing a timeout when
              * BOTTOM_OF_PIPE_TS is used as the workaround. This must be
              * emitted when the gfx queue is idle.